Patents by Inventor Naotaka Kuroda

Naotaka Kuroda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210132136
    Abstract: A method for measuring a current-voltage characteristic (Id-Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id-Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.
    Type: Application
    Filed: December 31, 2020
    Publication date: May 6, 2021
    Inventors: Tatsuya YANAGI, Hirotaka OTAKE, Hiroyuki SAKAIRI, Naotaka KURODA
  • Patent number: 10908204
    Abstract: A method for measuring a current-voltage characteristic (Id-Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id-Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: February 2, 2021
    Assignee: Rohm Co., Ltd.
    Inventors: Tatsuya Yanagi, Hirotaka Otake, Hiroyuki Sakairi, Naotaka Kuroda
  • Patent number: 10901024
    Abstract: A method for measuring a current-voltage characteristic (Id?Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id?Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: January 26, 2021
    Assignee: Rohm Co., Ltd.
    Inventors: Tatsuya Yanagi, Hirotaka Otake, Hiroyuki Sakairi, Naotaka Kuroda
  • Publication number: 20180233590
    Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).
    Type: Application
    Filed: March 16, 2018
    Publication date: August 16, 2018
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
  • Publication number: 20180188312
    Abstract: A method for measuring a current-voltage characteristic (Id?Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id?Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.
    Type: Application
    Filed: February 27, 2018
    Publication date: July 5, 2018
    Inventors: Tatsuya YANAGI, Hirotaka OTAKE, Hiroyuki SAKAIRI, Naotaka KURODA
  • Patent number: 9954087
    Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: April 24, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
  • Publication number: 20170285095
    Abstract: A method for measuring a current-voltage characteristic (Id-Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id-Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.
    Type: Application
    Filed: March 29, 2017
    Publication date: October 5, 2017
    Inventors: Tatsuya YANAGI, Hirotaka OTAKE, Hiroyuki SAKAIRI, Naotaka KURODA
  • Patent number: 9029333
    Abstract: The present invention provides a glucose decomposition-suppressed solid preparation for dialysis among powdery or granular preparations for dialysis containing acetate-free solid organic acids as pH adjusting agents. The present invention provides the solid preparation for dialysis containing electrolytes, glucose and pH adjusting agents characterized in that solid organic acids containing reduced amount of microparticles are used, and more specifically, characterized in that solid organic acids whose 20 or less percent of particles are 250 ?m or less in diameter, or solid organic acids whose 10 or less percent of particles are 150 ?m or less in diameter, are used. Preferably, the solid organic acid contained therein is citric acid.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: May 12, 2015
    Assignee: Advanced Renal Technologies, Inc.
    Inventors: Yoshihiro Sugiyama, Yuichi Iwai, Michito Sumikawa, Naotaka Kuroda
  • Publication number: 20140367743
    Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).
    Type: Application
    Filed: August 27, 2014
    Publication date: December 18, 2014
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
  • Patent number: 8853666
    Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: October 7, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
  • Patent number: 8476756
    Abstract: A semiconductor device includes a semiconductor element having a rectangular two-dimensional geometry and serving as a heat source, a first heat sink section including the semiconductor element mounted thereon, and a second heat sink section joined to an opposite side of the first heat sink section that includes the semiconductor element. A relation among directional components of thermal conductivity is K1yy?K1xx>K1zz, where directional components of a three-dimensional thermal conductivity of the heat sink section in X, Y, and Z directions are determined as Kxx, Kyy, and Kzz. A relation among directional components of a thermal conductivity of the second heat sink section is K2zz?K2yy>K2xx or K2yy?K2zz>K2xx, where the directional components of the thermal conductivity of the second heat sink section in X, Y, and X directions are determined as K2xx, K2yy, and K2zz.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: July 2, 2013
    Assignee: NEC Corporation
    Inventors: Naotaka Kuroda, Akio Wakejima, Masahiro Tanomura, Hironobu Miyamoto
  • Patent number: 8466495
    Abstract: Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0?y?1); a carrier supply layer 13 composed of AlxGa1-xN (0?x?1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x<NA×?×t [cm?2]<5.6×1013x, where x denotes an Al compositional ratio of said carrier supply layer, t denotes a thickness of said p-type layer, NA denotes an impurity concentration, and ? denotes an activation ratio.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: June 18, 2013
    Assignee: NEC Corporation
    Inventors: Yuji Ando, Hironobu Miyamoto, Tatsuo Nakayama, Yasuhiro Okamoto, Takashi Inoue, Yasuhiro Murase, Kazuki Ota, Akio Wakejima, Naotaka Kuroda
  • Patent number: 8332190
    Abstract: Characteristics of a circuit element are predicted accurately by taking account not only of the temperature variation due to self-heating of the element but also of temperature variation due to heat transmission from an adjoining heater element.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: December 11, 2012
    Assignee: NEC Corporation
    Inventors: Masahiro Tanomura, Naotaka Kuroda, Masafumi Kawanaka
  • Publication number: 20120217547
    Abstract: Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0?y?1); a carrier supply layer 13 composed of AlxGa1-xN (0?x?1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x<NA×?×t [cm?2]<5.6×1013x, where x denotes an Al compositional ratio of said carrier supply layer, t denotes a thickness of said p-type layer, NA denotes an impurity concentration, and ? denotes an activation ratio.
    Type: Application
    Filed: May 10, 2012
    Publication date: August 30, 2012
    Applicant: NEC CORPORATION
    Inventors: Yuji ANDO, Hironobu MIYAMOTO, Tatsuo NAKAYAMA, Yasuhiro OKAMOTO, Takashi INOUE, Yasuhiro MURASE, Kazuki OTA, Akio WAKEJIMA, Naotaka KURODA
  • Patent number: 8198652
    Abstract: Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0?y?1); a carrier supply layer 13 composed of AlxGa1-xN (0?x?1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x<NA×?×t [cm?2]<5.6×1013x, where x denotes an Al compositional ratio of the carrier supply layer, t denotes a thickness of the p-type layer, NA denotes an impurity concentration, and ? denotes an activation ratio.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: June 12, 2012
    Assignee: NEC Corporation
    Inventors: Yuji Ando, Hironobu Miyamoto, Tatsuo Nakayama, Yasuhiro Okamoto, Takashi Inoue, Yasuhiro Murase, Kazuki Ota, Akio Wakejima, Naotaka Kuroda
  • Publication number: 20120012995
    Abstract: A semiconductor device includes a semiconductor element having a rectangular two-dimensional geometry and serving as a heat source, a first heat sink section including the semiconductor element mounted thereon, and a second heat sink section joined to an opposite side of the first heat sink section that includes the semiconductor element. A relation among directional components of thermal conductivity is K1yy?K1xx>K1zz, where directional components of a three-dimensional thermal conductivity of the heat sink section in X, Y, and Z directions are determined as Kxx, Kyy, and Kzz. A relation among directional components of a thermal conductivity of the second heat sink section is K2zz?K2yy>K2xx or K2yy?K2zz>K2xx, where the directional components of the thermal conductivity of the second heat sink section in X, Y, and X directions are determined as K2xx, K2yy, and K2zz.
    Type: Application
    Filed: September 21, 2011
    Publication date: January 19, 2012
    Applicant: NEC CORPORATION
    Inventors: Naotaka Kuroda, Akio Wakejima, Masahiro Tanomura, Hironobu Miyamoto
  • Patent number: 8063484
    Abstract: A semiconductor device, comprising: a semiconductor element 20 having a rectangular two-dimensional geometry and serving as a heat source; and a heat sink section 25 having the semiconductor element 20 mounted thereon, wherein a relation among the directional components of said thermal conductivity is: Kzz?Kyy>Kxx, where directional components of three-dimensional thermal conductivity of the heat sink section 25 in X, Y and Z directions are determined as Kxx, Kyy and Kzz, and where the longer side direction of the semiconductor element 20 is defined as X direction, the shorter side direction thereof is defined as Y direction and the thickness direction is defined as Z direction.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: November 22, 2011
    Assignee: NEC Corporation
    Inventors: Naotaka Kuroda, Akio Wakejima, Masahiro Tanomura, Hironobu Miyamoto
  • Publication number: 20100224910
    Abstract: Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0?y?1); a carrier supply layer 13 composed of AlxGa1-xN (0?x?1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x<NA×?×t [cm?2]<5.6×1013x, where x denotes an Al compositional ratio of the carrier supply layer, t denotes a thickness of the p-type layer, NA denotes an impurity concentration, and ? denotes an activation ratio.
    Type: Application
    Filed: March 29, 2007
    Publication date: September 9, 2010
    Applicant: NEC Corporation
    Inventors: Yuji Ando, Hironobu Miyamoto, Tatsuo Nakayama, Yasuhiro Okamoto, Takashi Inoue, Yasuhiro Murase, Kazuki Ota, Akio Wakejima, Naotaka Kuroda
  • Patent number: 7741700
    Abstract: A semiconductor device having sufficiently high heat dissipation performance while inhibiting an increase in the area of a chip is provided. In semiconductor device 1, a plurality of HBTs 20 and a plurality of diodes 30 are one-dimensionally and alternately arranged on semiconductor substrate 10. Anode electrode 36 of diode 30 is connected to emitter electrode 27 of HBT 20 via common emitter wiring 42. Diode 30 works as heat dissipating elements dissipating to semiconductor substrate 10 the heat transmitted through common emitter wiring 42 from emitter electrode 27, and also works as a protection diode connected in parallel between an emitter and a collector of HBT 20.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: June 22, 2010
    Assignees: NEC Corporation, NEC Electronics Corporation
    Inventors: Naotaka Kuroda, Masahiro Tanomura, Naoto Kurosawa
  • Publication number: 20100120702
    Abstract: The present invention provides a glucose decomposition-suppressed solid preparation for dialysis among powdery or granular preparations for dialysis containing acetate-free solid organic acids as pH adjusting agents. The present invention provides the solid preparation for dialysis containing electrolytes, glucose and pH adjusting agents characterized in that solid organic acids containing reduced amount of microparticles are used, and more specifically, characterized in that solid organic acids whose 20 or less percent of particles are 250 ?m or less in diameter, or solid organic acids whose 10 or less percent of particles are 150 ?m or less in diameter, are used. Preferably, the solid organic acid contained therein is citric acid.
    Type: Application
    Filed: November 24, 2009
    Publication date: May 13, 2010
    Applicant: Ajinomoto Co., Inc.
    Inventors: Yoshihiro Sugiyama, Yuichi Iwai, Michito Sumikawa, Naotaka Kuroda