Patents by Inventor Naotaka Kuroda
Naotaka Kuroda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230090004Abstract: Semiconductor device includes: semiconductor elements electrically connected in parallel; pad portion electrically connected to the semiconductor elements; and terminal portion electrically connected to the pad portion. As viewed in thickness direction, the semiconductor elements are aligned along first direction perpendicular to the thickness direction. The pad portion includes closed region surrounded by three line segments each formed by connecting two of first, second and third vertex not disposed on the same straight line. As viewed in thickness direction, the first vertex overlaps with one semiconductor element located in outermost position in first sense of the first direction. As viewed in the thickness direction, the second vertex overlaps with one semiconductor element located in outermost position in second sense of the first direction. As viewed in the thickness direction, the third vertex is located on perpendicular bisector of the line segment connecting the first and second vertex.Type: ApplicationFiled: April 13, 2021Publication date: March 23, 2023Inventors: Yohei NAKAMURA, Naotaka KURODA, Atsushi YAMAGUCHI
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Publication number: 20210132136Abstract: A method for measuring a current-voltage characteristic (Id-Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id-Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.Type: ApplicationFiled: December 31, 2020Publication date: May 6, 2021Inventors: Tatsuya YANAGI, Hirotaka OTAKE, Hiroyuki SAKAIRI, Naotaka KURODA
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Patent number: 10908204Abstract: A method for measuring a current-voltage characteristic (Id-Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id-Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.Type: GrantFiled: March 29, 2017Date of Patent: February 2, 2021Assignee: Rohm Co., Ltd.Inventors: Tatsuya Yanagi, Hirotaka Otake, Hiroyuki Sakairi, Naotaka Kuroda
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Patent number: 10901024Abstract: A method for measuring a current-voltage characteristic (Id?Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id?Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.Type: GrantFiled: February 27, 2018Date of Patent: January 26, 2021Assignee: Rohm Co., Ltd.Inventors: Tatsuya Yanagi, Hirotaka Otake, Hiroyuki Sakairi, Naotaka Kuroda
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Publication number: 20180233590Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).Type: ApplicationFiled: March 16, 2018Publication date: August 16, 2018Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
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Publication number: 20180188312Abstract: A method for measuring a current-voltage characteristic (Id?Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id?Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.Type: ApplicationFiled: February 27, 2018Publication date: July 5, 2018Inventors: Tatsuya YANAGI, Hirotaka OTAKE, Hiroyuki SAKAIRI, Naotaka KURODA
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Patent number: 9954087Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).Type: GrantFiled: August 27, 2014Date of Patent: April 24, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
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Publication number: 20170285095Abstract: A method for measuring a current-voltage characteristic (Id-Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id-Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.Type: ApplicationFiled: March 29, 2017Publication date: October 5, 2017Inventors: Tatsuya YANAGI, Hirotaka OTAKE, Hiroyuki SAKAIRI, Naotaka KURODA
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Patent number: 9029333Abstract: The present invention provides a glucose decomposition-suppressed solid preparation for dialysis among powdery or granular preparations for dialysis containing acetate-free solid organic acids as pH adjusting agents. The present invention provides the solid preparation for dialysis containing electrolytes, glucose and pH adjusting agents characterized in that solid organic acids containing reduced amount of microparticles are used, and more specifically, characterized in that solid organic acids whose 20 or less percent of particles are 250 ?m or less in diameter, or solid organic acids whose 10 or less percent of particles are 150 ?m or less in diameter, are used. Preferably, the solid organic acid contained therein is citric acid.Type: GrantFiled: November 24, 2009Date of Patent: May 12, 2015Assignee: Advanced Renal Technologies, Inc.Inventors: Yoshihiro Sugiyama, Yuichi Iwai, Michito Sumikawa, Naotaka Kuroda
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Publication number: 20140367743Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).Type: ApplicationFiled: August 27, 2014Publication date: December 18, 2014Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
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Patent number: 8853666Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).Type: GrantFiled: October 25, 2006Date of Patent: October 7, 2014Assignee: Renesas Electronics CorporationInventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
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Patent number: 8476756Abstract: A semiconductor device includes a semiconductor element having a rectangular two-dimensional geometry and serving as a heat source, a first heat sink section including the semiconductor element mounted thereon, and a second heat sink section joined to an opposite side of the first heat sink section that includes the semiconductor element. A relation among directional components of thermal conductivity is K1yy?K1xx>K1zz, where directional components of a three-dimensional thermal conductivity of the heat sink section in X, Y, and Z directions are determined as Kxx, Kyy, and Kzz. A relation among directional components of a thermal conductivity of the second heat sink section is K2zz?K2yy>K2xx or K2yy?K2zz>K2xx, where the directional components of the thermal conductivity of the second heat sink section in X, Y, and X directions are determined as K2xx, K2yy, and K2zz.Type: GrantFiled: September 21, 2011Date of Patent: July 2, 2013Assignee: NEC CorporationInventors: Naotaka Kuroda, Akio Wakejima, Masahiro Tanomura, Hironobu Miyamoto
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Patent number: 8466495Abstract: Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0?y?1); a carrier supply layer 13 composed of AlxGa1-xN (0?x?1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x<NA×?×t [cm?2]<5.6×1013x, where x denotes an Al compositional ratio of said carrier supply layer, t denotes a thickness of said p-type layer, NA denotes an impurity concentration, and ? denotes an activation ratio.Type: GrantFiled: May 10, 2012Date of Patent: June 18, 2013Assignee: NEC CorporationInventors: Yuji Ando, Hironobu Miyamoto, Tatsuo Nakayama, Yasuhiro Okamoto, Takashi Inoue, Yasuhiro Murase, Kazuki Ota, Akio Wakejima, Naotaka Kuroda
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Patent number: 8332190Abstract: Characteristics of a circuit element are predicted accurately by taking account not only of the temperature variation due to self-heating of the element but also of temperature variation due to heat transmission from an adjoining heater element.Type: GrantFiled: December 13, 2007Date of Patent: December 11, 2012Assignee: NEC CorporationInventors: Masahiro Tanomura, Naotaka Kuroda, Masafumi Kawanaka
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Publication number: 20120217547Abstract: Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0?y?1); a carrier supply layer 13 composed of AlxGa1-xN (0?x?1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x<NA×?×t [cm?2]<5.6×1013x, where x denotes an Al compositional ratio of said carrier supply layer, t denotes a thickness of said p-type layer, NA denotes an impurity concentration, and ? denotes an activation ratio.Type: ApplicationFiled: May 10, 2012Publication date: August 30, 2012Applicant: NEC CORPORATIONInventors: Yuji ANDO, Hironobu MIYAMOTO, Tatsuo NAKAYAMA, Yasuhiro OKAMOTO, Takashi INOUE, Yasuhiro MURASE, Kazuki OTA, Akio WAKEJIMA, Naotaka KURODA
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Patent number: 8198652Abstract: Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0?y?1); a carrier supply layer 13 composed of AlxGa1-xN (0?x?1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x<NA×?×t [cm?2]<5.6×1013x, where x denotes an Al compositional ratio of the carrier supply layer, t denotes a thickness of the p-type layer, NA denotes an impurity concentration, and ? denotes an activation ratio.Type: GrantFiled: March 29, 2007Date of Patent: June 12, 2012Assignee: NEC CorporationInventors: Yuji Ando, Hironobu Miyamoto, Tatsuo Nakayama, Yasuhiro Okamoto, Takashi Inoue, Yasuhiro Murase, Kazuki Ota, Akio Wakejima, Naotaka Kuroda
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Publication number: 20120012995Abstract: A semiconductor device includes a semiconductor element having a rectangular two-dimensional geometry and serving as a heat source, a first heat sink section including the semiconductor element mounted thereon, and a second heat sink section joined to an opposite side of the first heat sink section that includes the semiconductor element. A relation among directional components of thermal conductivity is K1yy?K1xx>K1zz, where directional components of a three-dimensional thermal conductivity of the heat sink section in X, Y, and Z directions are determined as Kxx, Kyy, and Kzz. A relation among directional components of a thermal conductivity of the second heat sink section is K2zz?K2yy>K2xx or K2yy?K2zz>K2xx, where the directional components of the thermal conductivity of the second heat sink section in X, Y, and X directions are determined as K2xx, K2yy, and K2zz.Type: ApplicationFiled: September 21, 2011Publication date: January 19, 2012Applicant: NEC CORPORATIONInventors: Naotaka Kuroda, Akio Wakejima, Masahiro Tanomura, Hironobu Miyamoto
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Patent number: 8063484Abstract: A semiconductor device, comprising: a semiconductor element 20 having a rectangular two-dimensional geometry and serving as a heat source; and a heat sink section 25 having the semiconductor element 20 mounted thereon, wherein a relation among the directional components of said thermal conductivity is: Kzz?Kyy>Kxx, where directional components of three-dimensional thermal conductivity of the heat sink section 25 in X, Y and Z directions are determined as Kxx, Kyy and Kzz, and where the longer side direction of the semiconductor element 20 is defined as X direction, the shorter side direction thereof is defined as Y direction and the thickness direction is defined as Z direction.Type: GrantFiled: October 25, 2007Date of Patent: November 22, 2011Assignee: NEC CorporationInventors: Naotaka Kuroda, Akio Wakejima, Masahiro Tanomura, Hironobu Miyamoto
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Publication number: 20100224910Abstract: Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0?y?1); a carrier supply layer 13 composed of AlxGa1-xN (0?x?1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x<NA×?×t [cm?2]<5.6×1013x, where x denotes an Al compositional ratio of the carrier supply layer, t denotes a thickness of the p-type layer, NA denotes an impurity concentration, and ? denotes an activation ratio.Type: ApplicationFiled: March 29, 2007Publication date: September 9, 2010Applicant: NEC CorporationInventors: Yuji Ando, Hironobu Miyamoto, Tatsuo Nakayama, Yasuhiro Okamoto, Takashi Inoue, Yasuhiro Murase, Kazuki Ota, Akio Wakejima, Naotaka Kuroda
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Patent number: 7741700Abstract: A semiconductor device having sufficiently high heat dissipation performance while inhibiting an increase in the area of a chip is provided. In semiconductor device 1, a plurality of HBTs 20 and a plurality of diodes 30 are one-dimensionally and alternately arranged on semiconductor substrate 10. Anode electrode 36 of diode 30 is connected to emitter electrode 27 of HBT 20 via common emitter wiring 42. Diode 30 works as heat dissipating elements dissipating to semiconductor substrate 10 the heat transmitted through common emitter wiring 42 from emitter electrode 27, and also works as a protection diode connected in parallel between an emitter and a collector of HBT 20.Type: GrantFiled: March 30, 2005Date of Patent: June 22, 2010Assignees: NEC Corporation, NEC Electronics CorporationInventors: Naotaka Kuroda, Masahiro Tanomura, Naoto Kurosawa