Patents by Inventor Naoto Fujishima
Naoto Fujishima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240079275Abstract: A gate insulating film has a multilayer structure including a SiO2 film, a LaAlO3 film, and an Al2O3 film that are sequentially stacked, relative permittivity of the gate insulating film being optimized by the LaAlO3 film. In forming the LaAlO3 film constituting the gate insulating film, a La2O3 film and an Al2O3 film are alternately deposited repeatedly using an ALD method. The La2O3 film is deposited first, whereby during a POA performed thereafter, a sub-oxide of the surface of the SiO2 film is removed by a cleaning effect of lanthanum atoms in the La2O3 film. A temperature of the POA is suitably set in a range from 700 degrees C. to less than 900 degrees C.Type: ApplicationFiled: April 27, 2023Publication date: March 7, 2024Applicant: FUJI ELECTRIC CO., LTD.Inventors: Takashi TSUJI, Yuichi ONOZAWA, Naoto FUJISHIMA, Linhua HUANG, Johnny Kin On SIN
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Patent number: 9892919Abstract: A first nickel film is deposited inside a contact hole of an interlayer dielectric formed on an n+-type SiC substrate. Irradiation with a first laser is carried out, forming an Ohmic contact with a silicon carbide semiconductor. A second nickel film and a front surface electrode film are deposited on the first nickel film, forming a source electrode. The back surface of the n+-type SiC substrate is ground, and a third nickel film is formed on the ground back surface of the n+-type SiC substrate. Irradiation with a second laser is carried out, forming an Ohmic contact with the silicon carbide semiconductor. A fourth nickel film and a back surface electrode film are deposited on the third nickel film, forming a drain electrode. By so doing, it is possible to prevent electrical characteristic deterioration of a semiconductor device, and to prevent warping and cracking of a wafer.Type: GrantFiled: April 9, 2015Date of Patent: February 13, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Haruo Nakazawa, Masaaki Tachioka, Naoto Fujishima, Masaaki Ogino, Tsunehiro Nakajima, Kenichi Iguchi
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Publication number: 20150214053Abstract: A first nickel film is deposited inside a contact hole of an interlayer dielectric formed on an n+-type SiC substrate. Irradiation with a first laser is carried out, forming an Ohmic contact with a silicon carbide semiconductor. A second nickel film and a front surface electrode film are deposited on the first nickel film, forming a source electrode. The back surface of the n+-type SiC substrate is ground, and a third nickel film is formed on the ground back surface of the n+-type SiC substrate. Irradiation with a second laser is carried out, forming an Ohmic contact with the silicon carbide semiconductor. A fourth nickel film and a back surface electrode film are deposited on the third nickel film, forming a drain electrode. By so doing, it is possible to prevent electrical characteristic deterioration of a semiconductor device, and to prevent warping and cracking of a wafer.Type: ApplicationFiled: April 9, 2015Publication date: July 30, 2015Applicant: FUJI ELECTRIC CO., LTD.Inventors: Haruo NAKAZAWA, Masaaki TACHIOKA, Naoto FUJISHIMA, Masaaki OGINO, Tsunehiro NAKAJIMA, Kenichi IGUCHI
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Patent number: 8378418Abstract: A bidirectional Trench Lateral Power MOSFET (TLPM) can achieve a high breakdown voltage and a low on-resistance. A plurality of straight-shaped islands having circular portions at both ends are surrounded by a trench arrangement. The islands provide first n source regions and a second n source region is formed on the outside of the islands. With such a pattern, the breakdown voltage in the case where the first n source regions are at a high potential can be higher than the breakdown voltage in the case where the second n source region is at a high potential. Alternatively, in the case of not changing the breakdown voltage, the on-resistance can be reduced.Type: GrantFiled: August 26, 2010Date of Patent: February 19, 2013Assignee: Fuji Electric Co., Ltd.Inventors: Mutsumi Kitamura, Akio Sugi, Naoto Fujishima, Shinichiro Matsunaga
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Patent number: 8084812Abstract: A semiconductor device and a method of fabrication thereof includes a bidirectional device having a high breakdown voltage and a decreased ON voltage. An n-type extended drain region is formed in the bottom surface of each trench. A p-type offset region is formed in each split semiconductor region. First and second n-source regions are formed in the surface of the p-type offset region. This reduces the in-plane distance between the first and second n-source regions to thereby increase the density of cells. The breakdown voltage is maintained along the trenches. This increases the resistance to high voltages. Channels are formed in the sidewalls of the trenches by making the voltage across each gate electrode higher than the voltage across each of the first and second n-source electrodes. Thus, a bidirectional LMOSFET through which current flows in both directions is achieved. The LMOSFET has a high breakdown voltage and a decreased ON voltage.Type: GrantFiled: November 4, 2009Date of Patent: December 27, 2011Assignee: Fuji Electric Co., Ltd.Inventors: Mutsumi Kitamura, Naoto Fujishima
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Patent number: 7902596Abstract: A semiconductor device and a method of fabrication thereof includes a bidirectional device having a high breakdown voltage and a decreased ON voltage. An n-type extended drain region is formed in the bottom surface of each trench. A p-type offset region is formed in each split semiconductor region. First and second n-source regions are formed in the surface of the p-type offset region. This reduces the in-plane distance between the first and second n-source regions to thereby increase the density of cells. The breakdown voltage is maintained along the trenches. This increases the resistance to high voltages. Channels are formed in the sidewalls of the trenches by making the voltage across each gate electrode higher than the voltage across each of the first and second n-source electrodes. Thus, a bidirectional LMOSFET through which current flows in both directions is achieved. The LMOSFET has a high breakdown voltage and a decreased ON voltage.Type: GrantFiled: August 16, 2004Date of Patent: March 8, 2011Assignee: Fuji Electric Systems Co., Ltd.Inventors: Mutsumi Kitamura, Naoto Fujishima
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Publication number: 20100330398Abstract: A bidirectional Trench Lateral Power MOSFET (TLPM) can achieve a high breakdown voltage and a low on-resistance. A plurality of straight-shaped islands having circular portions at both ends are surrounded by a trench arrangement. The islands provide first n source regions and a second n source region is formed on the outside of the islands. With such a pattern, the breakdown voltage in the case where the first n source regions are at a high potential can be higher than the breakdown voltage in the case where the second n source region is at a high potential. Alternatively, in the case of not changing the breakdown voltage, the on-resistance can be reduced.Type: ApplicationFiled: August 26, 2010Publication date: December 30, 2010Applicant: Fuji Electric Systems Co., Ltd.Inventors: Mutsumi Kitamura, Akio Sugi, Naoto Fujishima, Shinichiro Matsunaga
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Patent number: 7800167Abstract: A bidirectional Trench Lateral Power MOSFET (TLPM) can achieve a high breakdown voltage and a low on-resistance. A plurality of straight-shaped islands having circular portions at both ends are surrounded by a trench arrangement. The islands provide first n source regions and a second n source region is formed on the outside of the islands. With such a pattern, the breakdown voltage in the case where the first n source regions are at a high potential can be higher than the breakdown voltage in the case where the second n source region is at a high potential. Alternatively, in the case of not changing the breakdown voltage, the on-resistance can be reduced.Type: GrantFiled: May 25, 2007Date of Patent: September 21, 2010Assignee: Fuji Electric Systems Co., Ltd.Inventors: Mutsumi Kitamura, Akio Sugi, Naoto Fujishima, Shinichiro Matsunaga
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Patent number: 7687385Abstract: The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region.Type: GrantFiled: March 2, 2007Date of Patent: March 30, 2010Assignee: Fuji Electric Holdings Co., Ltd.Inventors: Kazuo Matsuzaki, Naoto Fujishima, Akio Kitamura, Gen Tada, Masaru Saito
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Publication number: 20100044749Abstract: A semiconductor device and a method of fabrication thereof includes a bidirectional device having a high breakdown voltage and a decreased ON voltage. An n-type extended drain region is formed in the bottom surface of each trench. A p-type offset region is formed in each split semiconductor region. First and second n-source regions are formed in the surface of the p-type offset region. This reduces the in-plane distance between the first and second n-source regions to thereby increase the density of cells. The breakdown voltage is maintained along the trenches. This increases the resistance to high voltages. Channels are formed in the sidewalls of the trenches by making the voltage across each gate electrode higher than the voltage across each of the first and second n-source electrodes. Thus, a bidirectional LMOSFET through which current flows in both directions is achieved. The LMOSFET has a high breakdown voltage and a decreased ON voltage.Type: ApplicationFiled: November 4, 2009Publication date: February 25, 2010Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventors: Mutsumi KITAMURA, Naoto FUJISHIMA
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Patent number: 7476942Abstract: The SOI lateral semiconductor device includes a semiconductor region of a first conductivity type, a buried oxide film layer in the semiconductor region, a thin active layer on the buried oxide film layer, an anode region in the thin active layer, and a drain layer contacting the buried oxide film layer for confining the minority carriers injected from the anode region to the thin active layer within the thin active layer and for forming a structure that sustains a high breakdown voltage. The SOI lateral semiconductor device can provide a high breakdown voltage and low switching losses using the thin buried oxide film, which can be formed by an implanted oxygen (SIMOX) method.Type: GrantFiled: April 8, 2007Date of Patent: January 13, 2009Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Yasumasa Watanabe, Hideaki Teranishi, Naoto Fujishima
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Publication number: 20080303087Abstract: Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.Type: ApplicationFiled: April 24, 2008Publication date: December 11, 2008Applicant: FUJI ELECTRIC CO., LTD.Inventors: Akio Sugi, Naoto Fujishima, Mutsumi Kitamura, Katsuya Tabuchi, Setsuko Wakimoto
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Patent number: 7445982Abstract: A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an n-type expanded drain region, and a thick oxide film are formed. A second trench etching deepens the trench. Gate oxide films and gate electrodes of the TLPM, an NMOSFET, and a PMOSFET are formed. P-type base regions of the TLPM and an NPN bipolar transistor are formed. An n-type source and drain region of the TLPM, and n-type diffusion regions of the NMOSFET and the NPN bipolar transistor are formed. P-type diffusion regions of the PMOSFET and the NPN bipolar transistor are formed. An interlayer oxide film, a contact electrode, and constituent metal electrodes are formed.Type: GrantFiled: August 28, 2007Date of Patent: November 4, 2008Assignee: Fuji Electric Co., Ltd.Inventors: Naoto Fujishima, C. Andre T. Salama
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Patent number: 7445983Abstract: A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an n-type expanded drain region, and a thick oxide film are formed. A second trench etching deepens the trench. Gate oxide films and gate electrodes of the TLPM, an NMOSFET, and a PMOSFET are formed. P-type base regions of the TLPM and an NPN bipolar transistor are formed. An n-type source and drain region of the TLPM, and n-type diffusion regions of the NMOSFET and the NPN bipolar transistor are formed. P-type diffusion regions of the PMOSFET and the NPN bipolar transistor are formed. An interlayer oxide film, a contact electrode, and constituent metal electrodes are formed.Type: GrantFiled: August 28, 2007Date of Patent: November 4, 2008Assignee: Fuji Electric Co., Ltd.Inventors: Naoto Fujishima, C. Andre T. Salama
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Publication number: 20080135927Abstract: An insulated gate semiconductor device, specifically, a trench lateral MOSFET having improved hot carrier resistance can be provided without increasing the number of processes and device pitch and without degrading device breakdown voltages and on-resistance characteristics RonA. A junction depth Xj of a p base region of a TLPM (trench lateral power MOSFET) is made smaller than the depth of a trench, and the trench is formed with a depth Dt of about 1.2 ?m such that the junction does not contact a curved corner part at the bottom of the trench.Type: ApplicationFiled: November 21, 2007Publication date: June 12, 2008Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventors: Masaharu YAMAJI, Naoto FUJISHIMA, Mutsumi KITAMURA
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Patent number: 7365392Abstract: Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.Type: GrantFiled: December 14, 2004Date of Patent: April 29, 2008Assignee: Fuji Electric Co., Ltd.Inventors: Akio Sugi, Naoto Fujishima, Mutsumi Kitamura, Katsuya Tabuchi, Setsuko Wakimoto
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Patent number: 7344935Abstract: A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an n-type expanded drain region, and a thick oxide film are formed. A second trench etching deepens the trench. Gate oxide films and gate electrodes of the TLPM, an NMOSFET, and a PMOSFET are formed. P-type base regions of the TLPM and an NPN bipolar transistor are formed. An n-type source and drain region of the TLPM, and n-type diffusion regions of the NMOSFET and the NPN bipolar transistor are formed. P-type diffusion regions of the PMOSFET and the NPN bipolar transistor are formed. An interlayer oxide film, a contact electrode, and constituent metal electrodes are formed.Type: GrantFiled: August 18, 2004Date of Patent: March 18, 2008Assignee: Fuji Electric Co., Ltd.Inventors: Naoto Fujishima, C. Andre T. Salama
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Publication number: 20070298563Abstract: A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an n-type expanded drain region, and a thick oxide film are formed. A second trench etching deepens the trench. Gate oxide films and gate electrodes of the TLPM, an NMOSFET, and a PMOSFET are formed. P-type base regions of the TLPM and an NPN bipolar transistor are formed. An n-type source and drain region of the TLPM, and n-type diffusion regions of the NMOSFET and the NPN bipolar transistor are formed. P-type diffusion regions of the PMOSFET and the NPN bipolar transistor are formed. An interlayer oxide film, a contact electrode, and constituent metal electrodes are formed.Type: ApplicationFiled: August 28, 2007Publication date: December 27, 2007Applicant: Fuji Electric Co., Ltd.Inventors: Naoto Fujishima, C. Andre Salama
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Publication number: 20070298562Abstract: A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an n-type expanded drain region, and a thick oxide film are formed. A second trench etching deepens the trench. Gate oxide films and gate electrodes of the TLPM, an NMOSFET, and a PMOSFET are formed. P-type base regions of the TLPM and an NPN bipolar transistor are formed. An n-type source and drain region of the TLPM, and n-type diffusion regions of the NMOSFET and the NPN bipolar transistor are formed. P-type diffusion regions of the PMOSFET and the NPN bipolar transistor are formed. An interlayer oxide film, a contact electrode, and constituent metal electrodes are formed.Type: ApplicationFiled: August 28, 2007Publication date: December 27, 2007Applicant: Fui Electric Co., Ltd.Inventors: Naoto Fujishima, C.Andre Salama
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Publication number: 20070274110Abstract: A bidirectional Trench Lateral Power MOSFET (TLPM) can achieve a high breakdown voltage and a low on-resistance. A plurality of straight-shaped islands having circular portions at both ends are surrounded by a trench arrangement. The islands provide first n source regions and a second n source region is formed on the outside of the islands. With such a pattern, the breakdown voltage in the case where the first n source regions are at a high potential can be higher than the breakdown voltage in the case where the second n source region is at a high potential. Alternatively, in the case of not changing the breakdown voltage, the on-resistance can be reduced.Type: ApplicationFiled: May 25, 2007Publication date: November 29, 2007Applicant: Fuji Electric Device Technology Co., LtdInventors: Mutsumi Kitamura, Akio Sugi, Naoto Fujishima, Shinichiro Matsunaga