Patents by Inventor Naoto Kimura
Naoto Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20140226903Abstract: An image processing apparatus comprises a region discrimination unit configured to discriminate object regions included in an image; a first calculation unit configured to calculate representative luminance values of a plurality of object regions discriminated by the region discrimination unit; a second calculation unit configured to calculate luminance distribution information of each of the plurality of object regions discriminated by the region discrimination unit; a determination unit configured to determine tone characteristics based on the representative luminance values of the plurality of object regions calculated by the first calculation unit and the pieces of luminance distribution information of the plurality of object regions calculated by the second calculation unit; and an image processing unit configured to perform tone correction processing based on the tone characteristics determined by the determination unit.Type: ApplicationFiled: February 3, 2014Publication date: August 14, 2014Applicant: CANON KABUSHIKI KAISHAInventor: Naoto Kimura
-
Publication number: 20140218559Abstract: An image pickup apparatus capable of obtaining a natural image close to what is seen with eyes and broad in dynamic range. A plurality of object regions are determined based on image data, and representative brightness values of respective ones of the object regions are calculated. A first exposure condition is decided based on the representative brightness value of a first object region which is a main object region, and a second exposure condition is decided based on the representative brightness values of the first and second object regions. By using the first and second exposure conditions, a plurality of images for use in generating a synthesized image are acquired.Type: ApplicationFiled: January 30, 2014Publication date: August 7, 2014Applicant: CANON KABUSHIKI KAISHAInventors: Shota Yamaguchi, Naoto Kimura
-
Patent number: 8236620Abstract: To solve a problem in that a die processing cost increases when employing a method involving providing a suction hole in the die to fix an island onto a bottom surface, provided is a semiconductor device, which includes: a semiconductor chip, an island having a first surface, on which the semiconductor chip is mounted, and a second surface opposing to the first surface, a hanger pin extended from the island, a branch portion extended from one of the island and the hanger pin, and a resin encapsulating the semiconductor chip, the island, the hanger pin and the brunch portion while exposing the second surface of the island.Type: GrantFiled: April 6, 2011Date of Patent: August 7, 2012Assignee: Renesas Electronics CorporationInventor: Naoto Kimura
-
Publication number: 20120134538Abstract: An object tracking device capable of accurately tracking an object as a tracking target. The device receives an image signal having a plurality of frame images and tracks a specific object in the image signal. The device sets a predetermined number of small areas in a reference area indicative of an area where an image of the object is formed in the preceding frame image. The object tracking device detects a motion vector of the object in each of the small areas, and determines a change of the object according to the motion vector to thereby obtain shape change information. The device corrects the location and size of the reference area according to the shape change information to thereby correct the reference area to a corrected reference area, and tracks the object using the corrected reference area.Type: ApplicationFiled: November 22, 2011Publication date: May 31, 2012Applicant: CANON KABUSHIKI KAISHAInventor: Naoto KIMURA
-
Publication number: 20110183473Abstract: To solve a problem in that a die processing cost increases when employing a method involving providing a suction hole in the die to fix an island onto a bottom surface, provided is a semiconductor device, which includes: a semiconductor chip, an island having a first surface, on which the semiconductor chip is mounted, and a second surface opposing to the first surface, a hanger pin extended from the island, a branch portion extended from one of the island and the hanger pin, and a resin encapsulating the semiconductor chip, the island, the hanger pin and the brunch portion while exposing the second surface of the island.Type: ApplicationFiled: April 6, 2011Publication date: July 28, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Naoto KIMURA
-
Patent number: 7944027Abstract: To solve a problem in that a die processing cost increases when employing a method involving providing a suction hole in the die to fix an island onto a bottom surface, provided is a semiconductor device, which includes: a semiconductor chip, an island having a first surface, on which the semiconductor chip is mounted; and a second surface opposing to the first surface, a hanger pin extended from the island, a branch portion extended from one of the island and the hanger pin, and a resin encapsulating the semiconductor chip, the island, the hanger pin and the brunch portion while exposing the second surface of the island.Type: GrantFiled: March 14, 2008Date of Patent: May 17, 2011Assignee: Renesas Electronics CorporationInventor: Naoto Kimura
-
Patent number: 7705437Abstract: Disclosed herewith is a semiconductor device, which includes a semiconductor chip; a lead device that includes an island for mounting the semiconductor chip and having an area smaller than that of the semiconductor chip at its contact surface, as well as plural hanging leads for supporting the island and coming in contact partially with the semiconductor chip; a mounting material provided on a contact surface between each of the island and hanging leads and the semiconductor chip so as to adhere the semiconductor chip to the island and the hanging leads; and sealing resin for sealing the semiconductor chip. The modulus of elasticity of the mounting material is lower than that of the sealing resin. The mounting material is further coated on the back surfaces of the contact surfaces of the island and the hanging leads.Type: GrantFiled: October 14, 2008Date of Patent: April 27, 2010Assignee: NEC Electronics CorporationInventor: Naoto Kimura
-
Patent number: 7521778Abstract: There is provided a semiconductor device 100 by which flexibility in interconnection design may be improved. The semiconductor device 100 includes: a lead frame 102 provided with an island 101 and a plurality of lead units 104; a first chip 109 which is mounted on the island 101 at the chip installed surface of the lead frame 102, and, at the same time, is provided with a first conductive pad 117 on the back of a surface opposing to the island 101; a conductive upper wire 113 connecting the first pad 117 and the lead unit 104; a conductive lower wire 115 connecting one lead unit 104 and another lead unit 104 among a plurality of the lead unit 104; and sealing resin 105 which seals the first chip 109.Type: GrantFiled: November 9, 2006Date of Patent: April 21, 2009Assignee: NEC Electronics CorporationInventor: Naoto Kimura
-
Publication number: 20090096074Abstract: Disclosed herewith is a semiconductor device, which includes a semiconductor chip; a lead device that includes an island for mounting the semiconductor chip and having an area smaller than that of the semiconductor chip at its contact surface, as well as plural hanging leads for supporting the island and coming in contact partially with the semiconductor chip; a mounting material provided on a contact surface between each of the island and hanging leads and the semiconductor chip so as to adhere the semiconductor chip to the island and the hanging leads; and sealing resin for sealing the semiconductor chip. The modulus of elasticity of the mounting material is lower than that of the sealing resin. The mounting material is further coated on the back surfaces of the contact surfaces of the island and the hanging leads.Type: ApplicationFiled: October 14, 2008Publication date: April 16, 2009Applicant: NEC Electronics CorporationInventor: Naoto Kimura
-
Publication number: 20080258318Abstract: Disclosed herewith is a semiconductor device capable of suppressing the peeling-off that might occur between an island and a resin layer due to a difference of the shrinkage between those items, thereby the reliability of the semiconductor device is improved. The semiconductor device of the present invention includes an island, a semiconductor chip mounted on the island, and a resin layer that seals the island and the semiconductor chip respectively. And at the interface between the island and the resin layer is provided a buffer film having an elastic modulus lower than that of the resin layer.Type: ApplicationFiled: April 18, 2008Publication date: October 23, 2008Applicant: NEC Electronics CorporationInventor: Naoto Kimura
-
Patent number: 7432588Abstract: A semiconductor device 100 comprises a leadframe 104 having an island portion 102; two chips of a first semiconductor chip 110 and a second semiconductor chip 120, respectively having top surfaces having, in the peripheral areas thereof, pad portions respectively having a plurality of first bonding pads 112 and second bonding pads 122 arranged therein and a back surface, being placed respectively on both surfaces of the island portion 102 of the leadframe 104 so as to oppose the back surface sides thereof to the island portion 102; and a mold resin 150 molding two these first semiconductor chip 110 and second semiconductor chip 120, wherein two these first semiconductor chip 110 and second semiconductor chip 120 have nearly same configurations of the pad portions; and two these semiconductor chips are arranged so as to shift the pad portions from each other.Type: GrantFiled: October 5, 2005Date of Patent: October 7, 2008Assignee: NEC Electronics CorporationInventor: Naoto Kimura
-
Publication number: 20080224280Abstract: To solve a problem in that a die processing cost increases when employing a method involving providing a suction hole in the die to fix an island onto a bottom surface, provided is a semiconductor device, which includes: a semiconductor chip, an island having a first surface, on which the semiconductor chip is mounted; and a second surface opposing to the first surface, a hanger pin extended from the island, a branch portion extended from one of the island and the hanger pin, and a resin encapsulating the semiconductor chip, the island, the hanger pin and the brunch portion while exposing the second surface of the island.Type: ApplicationFiled: March 14, 2008Publication date: September 18, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Naoto KIMURA
-
Publication number: 20080038872Abstract: Provided are a semiconductor device capable of mounting a plurality of semiconductor chips in compact on a leadframe and reducing manufacturing costs, and a method of manufacturing the same.Type: ApplicationFiled: August 6, 2007Publication date: February 14, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Naoto Kimura
-
Publication number: 20070108570Abstract: There is provided a semiconductor device 100 by which flexibility in interconnection design may be improved. The semiconductor device 100 includes: a lead frame 102 provided with an island 101 and a plurality of lead units 104; a first chip 109 which is mounted on the island 101 at the chip installed surface of the lead frame 102, and, at the same time, is provided with a first conductive pad 117 on the back of a surface opposing to the island 101; a conductive upper wire 113 connecting the first pad 117 and the lead unit 104; a conductive lower wire 115 connecting one lead unit 104 and another lead unit 104 among a plurality of the lead unit 104; and sealing resin 105 which seals the first chip 109.Type: ApplicationFiled: November 9, 2006Publication date: May 17, 2007Applicant: NEC ELECTRONICS CORPORATIONInventor: Naoto Kimura
-
Publication number: 20060138614Abstract: A semiconductor device 100 comprises a leadframe 104 having an island portion 102; two chips of a first semiconductor chip 110 and a second semiconductor chip 120, respectively having top surfaces having, in the peripheral areas thereof, pad portions respectively having a plurality of first bonding pads 112 and second bonding pads 122 arranged therein and a back surface, being placed respectively on both surfaces of the island portion 102 of the leadframe 104 so as to oppose the back surface sides thereof to the island portion 102; and a mold resin 150 molding two these first semiconductor chip 110 and second semiconductor chip 120, wherein two these first semiconductor chip 110 and second semiconductor chip 120 have nearly same configurations of the pad portions; and two these semiconductor chips are arranged so as to shift the pad portions from each other.Type: ApplicationFiled: October 5, 2005Publication date: June 29, 2006Applicant: NEC ELECTRONICS CORPORATIONInventor: Naoto Kimura
-
Patent number: 7030505Abstract: A resin-sealed type semiconductor device has a mount stage, a semiconductor chip mounted on the stage such that a rear surface of the chip is in contact with the stage, a heat spreader associated with the stage and the chip, and a molded resin package encapsulating the stage, chip, and heat spreader. The stage is configured such that the rear surface of the chip is partially covered with the stage, whereby uncovered areas are defined on the rear surface of the electronic component. The heat spreader is complementarily configured with respect to the stage so as to be in direct contact with the uncovered areas of the rear surface of the electronic component, whereby an entire thickness of both the mount stage and the heat spreader is smaller than a total of a thickness of the mount stage and a thickness of the heat spreader.Type: GrantFiled: November 6, 2003Date of Patent: April 18, 2006Assignee: NEC Electronics CorporationInventor: Naoto Kimura
-
Patent number: 6984889Abstract: The semiconductor device according to the present invention is equipped with a plurality of electronic circuits including at least one semiconductor integrated circuit chip, and a plurality of intermediate substrates interposed between the electronic components and a package and mounting the electronic components directly on its one major face, where each of the electronic component has on the one major face at least a plurality of first electrodes connected to the electronic components, a plurality of second electrodes for external connection, and internal connection electrodes for connecting between the electronic components including the connection between the first electrodes and the second electrodes that are mutually corresponding.Type: GrantFiled: April 19, 2004Date of Patent: January 10, 2006Assignee: NEC Electronics CorporationInventor: Naoto Kimura
-
Patent number: 6933612Abstract: A semiconductor device for an improved heatsink structure. The semiconductor device is composed of a first substrate, a first heatsink plate connected to the first substrate, a second substrate having a rear surfaces connected to the first heatsink plate, a semiconductor chip having a main surface bonded to a main surface of the second substrate, and a second heatsink plate connected to a rear surface of the semiconductor chip.Type: GrantFiled: October 17, 2003Date of Patent: August 23, 2005Assignee: NEC Electronics CorporationInventor: Naoto Kimura
-
Publication number: 20040195682Abstract: The semiconductor device according to the present invention is equipped with a plurality of electronic circuits including at least one semiconductor integrated circuit chip, and a plurality of intermediate substrates interposed between the electronic components and a package and mounting the electronic components directly on its one major face, where each of the electronic component has on the one major face at least a plurality of first electrodes connected to the electronic components, a plurality of second electrodes for external connection, and internal connection electrodes for connecting between the electronic components including the connection between the first electrodes and the second electrodes that are mutually corresponding.Type: ApplicationFiled: April 19, 2004Publication date: October 7, 2004Inventor: Naoto Kimura
-
Patent number: 6779702Abstract: In a wire bonding apparatus including a horn driver for generating ultrasonic waves, a capillary, an ultrasonic horn formed by a symmetrical section fixed to the horn driver and an asymmetrical section having an end for mounting the capillary, the asymmetrical section is constructed by a spurious vibration suppressing structure for suppressing a vibration component of the ultrasonic horn perpendicular to a propagation direction of the ultrasonic waves with the ultrasonic horn.Type: GrantFiled: January 24, 2003Date of Patent: August 24, 2004Assignee: NEC Electronics CorporationInventors: Naoto Kimura, Hidemi Matsukuma