Patents by Inventor Naoto Kusumoto

Naoto Kusumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190283186
    Abstract: A laser processing apparatus and a stack processing apparatus are provided. The laser processing apparatus includes a laser oscillator and an optical system for forming a linear beam and an x-y-? or x-? stage. With use of the x-y-? or x-? stage, the object to be processed can be moved and rotated in the horizontal direction. With this operation, a desired region of the object to be processed can be efficiently irradiated with laser light, and the area occupied by a chamber provided with the x-y-? or x-? stage can be made small.
    Type: Application
    Filed: October 26, 2017
    Publication date: September 19, 2019
    Inventors: Shunpei YAMAZAKI, Naoto KUSUMOTO
  • Patent number: 10394069
    Abstract: A display device includes a first region and a second region adjacent to the first region. A display element included in the first region has a function of reflecting visible light and a function of emitting visible light. A display element included in the second region has a function of emitting visible light. In an electronic device including the display device, the first region is located on a first surface (e.g., top surface) on which a main image is displayed, and the second region is located on a second surface (e.g., side surface) on which an auxiliary image is displayed.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: August 27, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Kubota, Naoto Kusumoto
  • Patent number: 10388687
    Abstract: An imaging device having a three-dimensional integration structure is provided. A first structure including a transistor including silicon in an active layer or an active region and a second structure including an oxide semiconductor in an active layer are fabricated. After that, the first and second structures are bonded to each other so that metal layers included in the first and second structures are bonded to each other; thus, an imaging device having a three-dimensional integration structure is formed.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: August 20, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Ikeda, Naoto Kusumoto
  • Patent number: 10373991
    Abstract: An imaging device with low power consumption is provided. The pixel of the imaging device includes first and second photoelectric conversion elements, and first to fifth transistors. A cathode of the first photoelectric conversion element is electrically connected to the first transistor. An anode of a second photoelectric conversion element is electrically connected to the second transistor. Imaging data of a reference frame is obtained using the first photoelectric conversion element, and then imaging data of a difference detection frame is obtained using the second photoelectric conversion element. After the imaging data of the difference detection frame is obtained, a first potential that is a potential of a signal output from the pixel and a second potential that is a reference potential are compared. Whether or not there is a difference between the imaging data of the reference frame and the imaging data of the difference detection frame is determined using the first potential and the second potential.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: August 6, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuro Ohmaru, Naoto Kusumoto, Kentaro Hayashi
  • Publication number: 20190147312
    Abstract: Thin film integrated circuits are peeled from a substrate and the peeled thin film integrated circuits are sealed, efficiently in order to improve manufacturing yields. The present invention provides laminating system comprising transporting means for transporting a substrate provided with a plurality of thin film integrated circuits; first peeling means for bonding first surfaces of the thin film integrated circuits to a first sheet member to peel the thin film integrated circuits from the substrate; second peeling means for bonding second surfaces of the thin film integrated circuits to a second sheet member to peel the thin film integrated circuits from the first sheet member; and sealing means for interposing the thin film integrated circuits between the second sheet member and a third sheet member to seal the thin film integrated circuit with the second sheet member and the third sheet member.
    Type: Application
    Filed: January 15, 2019
    Publication date: May 16, 2019
    Inventors: Ryosuke WATANABE, Naoto KUSUMOTO, Osamu NAKAMURA
  • Patent number: 10109667
    Abstract: An imaging device that has a structure where a transistor is used in common by a plurality of pixels and is capable of imaging with a global shutter system is provided. A transistor that resets the potential of a charge detection portion, a transistor that outputs a signal corresponding to the potential of the charge detection portion, and a transistor that selects a pixel are used in common by the plurality of pixels. A transistor is provided between a power supply line and a photoelectric conversion element. Exposure is performed by turning on the transistor. Imaging data is retained in a charge retention portion by turning off the transistor.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: October 23, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Naoto Kusumoto
  • Publication number: 20180233525
    Abstract: An imaging device having a three-dimensional integration structure is provided. A first structure including a transistor including silicon in an active layer or an active region and a second structure including an oxide semiconductor in an active layer are fabricated. After that, the first and second structures are bonded to each other so that metal layers included in the first and second structures are bonded to each other; thus, an imaging device having a three-dimensional integration structure is formed.
    Type: Application
    Filed: April 9, 2018
    Publication date: August 16, 2018
    Inventors: Takayuki IKEDA, Naoto KUSUMOTO
  • Patent number: 10020336
    Abstract: An imaging device having a three-dimensional integration structure is provided. A first structure including a transistor including silicon in an active layer or an active region and a second structure including an oxide semiconductor in an active layer are fabricated. After that, the first and second structures are bonded to each other so that metal layers included in the first and second structures are bonded to each other; thus, an imaging device having a three-dimensional integration structure is formed.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: July 10, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Ikeda, Naoto Kusumoto
  • Publication number: 20180077408
    Abstract: A display system which enables a stereoscopic image to be perceived by the naked eye is provided. The display system includes a display panel which can display a first image, a second image, a third image, and a fourth image. The first image has a region overlapping with the third image. The second image has a region overlapping with the fourth image. The first image and the third image are perceived by one of the right and left eyes and the second image and the fourth image are perceived by the other of the right and left eyes, so that a composite image of the first to fourth images is stereoscopically perceivable.
    Type: Application
    Filed: September 12, 2017
    Publication date: March 15, 2018
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akio Suzuki, Naoto Kusumoto
  • Patent number: 9881954
    Abstract: An imaging device with high imaging quality capable of being manufactured at low cost is provided. The imaging device includes a first transistor, a second transistor, a third transistor, a fourth transistor, a photodiode, and a capacitor. Each of the first to the fourth transistors includes a first gate electrode and a second gate electrode, and the second gate electrode of each of the first to the fourth transistors and one electrode of the capacitor are electrically connected to an anode electrode of the photodiode.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: January 30, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hironobu Takahashi, Yukinori Shima, Kengo Akimoto, Junichi Koezuka, Naoto Kusumoto
  • Publication number: 20180026037
    Abstract: A display device with a narrow bezel is provided. The display device includes a pixel circuit and a driver circuit which are provided on the same plane. The driver circuit includes a selection circuit and a buffer circuit. The selection circuit includes a first transistor. The buffer circuit includes a second transistor. The first transistor has a region overlapping with the second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. One of a source and a drain of the second transistor is electrically connected to the pixel circuit.
    Type: Application
    Filed: July 19, 2017
    Publication date: January 25, 2018
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Shishido, Naoto KUSUMOTO
  • Publication number: 20170357113
    Abstract: A display device includes a first region and a second region adjacent to the first region. A display element included in the first region has a function of reflecting visible light and a function of emitting visible light. A display element included in the second region has a function of emitting visible light. In an electronic device including the display device, the first region is located on a first surface (e.g., top surface) on which a main image is displayed, and the second region is located on a second surface (e.g., side surface) on which an auxiliary image is displayed.
    Type: Application
    Filed: June 7, 2017
    Publication date: December 14, 2017
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke KUBOTA, Naoto KUSUMOTO
  • Patent number: 9837551
    Abstract: Provided is a semiconductor device that can be miniaturized in a simple process and that can prevent deterioration of electrical characteristics due to miniaturization. The semiconductor device includes an oxide semiconductor layer, a first conductor in contact with the oxide semiconductor layer, and an insulator in contact with the first conductor. Further, an opening portion is provided in the oxide semiconductor layer, the first conductor, and the insulator. In the opening portion, side surfaces of the oxide semiconductor layer, the first conductor, and the insulator are aligned, and the oxide semiconductor layer and the first conductor are electrically connected to a second conductor by side contact.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: December 5, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Suguru Hondo, Kazuya Hanaoka, Shinya Sasagawa, Naoto Kusumoto
  • Publication number: 20170330973
    Abstract: A laser processing apparatus and a stack processing apparatus are provided. The laser processing apparatus can perform steps selectively by switching of optical paths. The steps are a step in which a first surface of a flat-plate structure is irradiated with a laser and a step in which a surface opposite to the first surface of the structure is irradiated with the laser. The laser is a linear laser whose shape on the irradiated surface is a rectangle. By laser irradiation performed while the structure is moved in the horizontal direction, the whole or a desired region of the first surface or the opposite surface of the structure can be processed.
    Type: Application
    Filed: May 8, 2017
    Publication date: November 16, 2017
    Inventors: Shunpei YAMAZAKI, Yoshiharu HIRAKATA, Naoto KUSUMOTO
  • Patent number: 9761749
    Abstract: A photoelectric conversion device with improved electric characteristics is provided. The photoelectric conversion device has a structure in which a window layer is formed by a stack of a first silicon semiconductor layer and a second silicon semiconductor layer, and the second silicon semiconductor layer has high carrier concentration than the first silicon semiconductor layer and has an opening. Light irradiation is performed on the first silicon semiconductor layer through the opening without passing through the second silicon semiconductor layer; thus, light absorption loss in the window layer can be reduced.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: September 12, 2017
    Assignee: Semiconductor Energy Laboratory Co., LTD.
    Inventors: Takashi Hirose, Naoto Kusumoto
  • Publication number: 20170250156
    Abstract: An imaging system using ultraviolet light or a manufacturing apparatus including the imaging system is provided. An imaging system includes an imaging element and a light source, which operates the imaging element with light that is emitted from the light source and reflected or transmitted by an object. A pixel included in the imaging element includes a photoelectric conversion element and a charge holding part. The light source has a function of emitting ultraviolet light to an object. The photoelectric conversion element is irradiated with the ultraviolet light reflected or transmitted by the object. The photoelectric conversion element has a function of changing the potential of the charge holding part when irradiated with the ultraviolet light and retaining the potential when not irradiated with the ultraviolet light.
    Type: Application
    Filed: February 16, 2017
    Publication date: August 31, 2017
    Inventors: Akio ENDO, Yusuke YOSHITANI, Jun KOYAMA, Naoto KUSUMOTO
  • Patent number: 9722055
    Abstract: A semiconductor device with a structure in which an increase in the number of oxygen vacancies in an oxide semiconductor layer can be suppressed and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an oxide insulating layer; intermediate layers apart from each other over the oxide insulating layer; a source electrode layer and a drain electrode layer over the intermediate layers; an oxide semiconductor layer that is electrically connected to the source electrode layer and the drain electrode layer and is in contact with the oxide insulating layer; a gate insulating film over the source electrode layer, the drain electrode layer, and the oxide semiconductor layer; and a gate electrode layer that is over the gate insulating film and overlaps with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: August 1, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuya Hanaoka, Naoto Kusumoto
  • Publication number: 20170186800
    Abstract: An imaging device having a three-dimensional integration structure is provided. A first structure including a transistor including silicon in an active layer or an active region and a second structure including an oxide semiconductor in an active layer are fabricated. After that, the first and second structures are bonded to each other so that metal layers included in the first and second structures are bonded to each other; thus, an imaging device having a three-dimensional integration structure is formed.
    Type: Application
    Filed: December 19, 2016
    Publication date: June 29, 2017
    Inventors: Takayuki IKEDA, Naoto KUSUMOTO
  • Publication number: 20170104025
    Abstract: An imaging device that has a structure where a transistor is used in common by a plurality of pixels and is capable of imaging with a global shutter system is provided. A transistor that resets the potential of a charge detection portion, a transistor that outputs a signal corresponding to the potential of the charge detection portion, and a transistor that selects a pixel are used in common by the plurality of pixels. A transistor is provided between a power supply line and a photoelectric conversion element. Exposure is performed by turning on the transistor. Imaging data is retained in a charge retention portion by turning off the transistor.
    Type: Application
    Filed: September 29, 2016
    Publication date: April 13, 2017
    Inventor: Naoto KUSUMOTO
  • Publication number: 20170084649
    Abstract: An imaging device that has a structure where a transistor is used in common by a plurality of pixels and is capable of imaging with a global shutter system is provided. A transistor that resets the potential of a charge detection portion, a transistor that outputs a signal corresponding to the potential of the charge detection portion, and a transistor that selects a pixel are used in common by the plurality of pixels. A node AN (a first charge retention portion), a node FD (a second charge retention portion), and a node FDX (the charge detection portion) are provided. Imaging data obtained in the node AN is transferred to the node FD, and the imaging data is sequentially transferred from the node FD to the node FDX to be read.
    Type: Application
    Filed: September 7, 2016
    Publication date: March 23, 2017
    Inventors: Takuro OHMARU, Naoto KUSUMOTO