Patents by Inventor Naoya Okada

Naoya Okada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240078347
    Abstract: A computer includes a processor including a plurality of registers, a memory, and a storage medium. A processor of a computer is configured to execute an encryption process of generating encrypted user data including a plurality of encrypted data blocks using the plurality of registers, and add a DIF including CRC to the encrypted data blocks and store the result in a storage medium. The encryption process includes repeatedly executing a first process of reading partial data from a predetermined number of the data blocks and storing the partial data in a first register, a second process of storing encrypted partial data obtained by encrypting the partial data stored in the first register in a second register, and a third process of executing an operation for calculating CRC using the encrypted partial data stored in the second register and storing a result of the operation in a third register.
    Type: Application
    Filed: February 21, 2023
    Publication date: March 7, 2024
    Inventors: Nagamasa MIZUSHIMA, Yoshihiro YOSHII, Naoya OKADA
  • Publication number: 20240069761
    Abstract: A storage system includes a storage controller and a plurality of storage drives. The storage controller holds power management information for managing power supplied to the storage system and power consumption of an operating mounted device of the storage system, and definition information for defining a relationship between power states and power consumption of the plurality of storage drives. The storage controller determines a power budget that can be supplied to the plurality of storage drives, based on the power management information according to a change in a configuration of the storage system, and determines a power state of each of the plurality of storage drives based on the power budget and the definition information.
    Type: Application
    Filed: March 7, 2023
    Publication date: February 29, 2024
    Applicant: Hitachi, Ltd.
    Inventors: Naoya OKADA, Kentaro SHIMADA, Yuki KOTAKE, Yukiyoshi TAKAMURA
  • Patent number: 11895458
    Abstract: A headband portion for headphones includes a headband spring configured to be bent in a substantially semicircular arc shape so as to be expandable so that a central portion of the headband spring is disposed in a vicinity of a head top portion of a wearer and a pair of both end portions of the headband spring are arranged on both side head portions of the wearer in response to the headphones being placed on the wearer's head, a pair of holding members configured to hold the both end portions by inserting the both end portions thereinto, and a pair of stepped screws that passes through both end side portions of the headband spring in a plate thickness direction of the headband spring and that holds the headband spring movably in an axial direction of the pair of stepped screws with gaps between flange portions of the pair of stepped screws and the holding members.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: February 6, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Naoya Okada, Tetsuhiro Akiyoshi
  • Publication number: 20230397366
    Abstract: A cooling apparatus includes a first vapor chamber which is formed of a combination of a first plate that receives heat from a heat source and a second plate facing the first plate, a liquid cooling section which includes a liquid cooling container combined with the first vapor chamber, and a plurality of first fins which are provided in the liquid cooling section and form a part of a channel of the liquid refrigerant. The second plate has a first inner surface constituting region which is located at the outer surface of the second plate and forms at least a part of a first inner surface of the liquid cooling section. The plurality of first fins are disposed in the first inner surface constituting region. The liquid cooling section has an introduction port and a discharge port.
    Type: Application
    Filed: June 7, 2023
    Publication date: December 7, 2023
    Inventors: Naoya OKADA, Takahiro MIYATA
  • Patent number: 11816336
    Abstract: The present disclosure is to optimize processes in a storage system. A storage system includes: a first controller including a first computing device and a first memory; a second controller including a second computing device and a second memory; and an interface circuit that transfers data between the first controller and the second controller. The interface circuit reads first compressed data from the second memory. The interface circuit decompresses the first compressed data to generate first uncompressed data, and writes the first uncompressed data into the first memory.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: November 14, 2023
    Assignee: HITACHI, LTD.
    Inventors: Naoya Okada, Takashi Nagao, Kentaro Shimada, Ryosuke Tatsumi, Sadahiro Sugimoto
  • Patent number: 11782603
    Abstract: A bandwidth between a second processor and a second memory is higher than a bandwidth between a first processor and a first memory. The first memory stores a read command from a host computer. The first processor analyzes a content of the read command, and in accordance with a result of the analysis, requests read data from the second processor. In response to the request from the first processor, the second processor reads the read data from one or more storage drives and stores the read data in the second memory. The second processor notifies the first processor that the read data is stored in the second memory. The first processor transfers the read data read from the second memory, to the host computer without storing the read data in the first memory.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: October 10, 2023
    Assignee: Hitachi, Ltd.
    Inventors: Kentaro Shimada, Takashi Nagao, Naoya Okada
  • Publication number: 20230318709
    Abstract: A nonlinearity compensation circuit includes a detector that detects a combination of input levels of a plurality of input signals, a memory that saves a correction value information item to compensate for nonlinear distortion, the correction value information item being saved corresponding to the combination of the input levels, and a compensator that corrects a target signal among said plurality of input signals using the correction value information item acquired from the memory based on the combination of the input levels detected by the detector.
    Type: Application
    Filed: December 27, 2022
    Publication date: October 5, 2023
    Applicant: Fujitsu Limited
    Inventors: Hisao NAKASHIMA, Naoya OKADA
  • Publication number: 20230136735
    Abstract: The present disclosure is to optimize processes in a storage system. A storage system includes: a first controller including a first computing device and a first memory; a second controller including a second computing device and a second memory; and an interface circuit that transfers data between the first controller and the second controller. The interface circuit reads first compressed data from the second memory. The interface circuit decompresses the first compressed data to generate first uncompressed data, and writes the first uncompressed data into the first memory.
    Type: Application
    Filed: December 19, 2022
    Publication date: May 4, 2023
    Inventors: Naoya OKADA, Takashi NAGAO, Kentaro SHIMADA, Ryosuke TATSUMI, Sadahiro SUGIMOTO
  • Publication number: 20230075635
    Abstract: A bandwidth between a second processor and a second memory is higher than a bandwidth between a first processor and a first memory. The first memory stores a read command from a host computer. The first processor analyzes a content of the read command, and in accordance with a result of the analysis, requests read data from the second processor. In response to the request from the first processor, the second processor reads the read data from one or more storage drives and stores the read data in the second memory. The second processor notifies the first processor that the read data is stored in the second memory. The first processor transfers the read data read from the second memory, to the host computer without storing the read data in the first memory.
    Type: Application
    Filed: March 9, 2022
    Publication date: March 9, 2023
    Inventors: Kentaro SHIMADA, Takashi NAGAO, Naoya OKADA
  • Publication number: 20230006453
    Abstract: A power storage device (4) includes a power storage unit (1211) including a plurality of cells, and a BMU (1212) configured to control the power storage unit (1211). The BMU (1212) includes an upper limit power acquisition unit (23) configured to acquire, based on a SOC and a temperature of the power storage unit (1211), an upper limit power that is an upper limit of a power output from the power storage unit (1211) or a power input to the power storage unit (1211).
    Type: Application
    Filed: December 11, 2020
    Publication date: January 5, 2023
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Naoya OKADA, Jyunichiro ABE, Takashi FUJIYAMA
  • Patent number: 11543972
    Abstract: The present disclosure is to optimize processes in a storage system. A storage system includes: a first controller including a first computing device and a first memory; a second controller including a second computing device and a second memory; and an interface circuit that transfers data between the first controller and the second controller. The interface circuit reads first compressed data from the second memory. The interface circuit decompresses the first compressed data to generate first uncompressed data, and writes the first uncompressed data into the first memory.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: January 3, 2023
    Assignee: HITACHI, LTD.
    Inventors: Naoya Okada, Takashi Nagao, Kentaro Shimada, Ryosuke Tatsumi, Sadahiro Sugimoto
  • Publication number: 20220396930
    Abstract: To provide a pipe member being able to reduce the vibration applied and improve its durability. A pipe member to be installed on the body of a construction machine has an outer main pipe and an inner auxiliary pipe inserted into the outer main pipe. An outer diameter of the inner auxiliary pipe is formed smaller than an inner diameter of the outer main pipe. The inner auxiliary pipe has a securing part secured on the outer main pipe and at least one of end parts of the inner auxiliary pipe is a free end without being secured on the outer main pipe.
    Type: Application
    Filed: October 8, 2019
    Publication date: December 15, 2022
    Applicant: Caterpillar SARL
    Inventors: Hidetaka ISHIZUKA, Kazumasa MATSUMURA, Naoya OKADA, Takafumi TADASU
  • Publication number: 20220386008
    Abstract: A headband portion for headphones includes a headband spring configured to be bent in a substantially semicircular arc shape so as to be expandable so that a central portion of the headband spring is disposed in a vicinity of a head top portion of a wearer and a pair of both end portions of the headband spring are arranged on both side head portions of the wearer in response to the headphones being placed on the wearer's head, a pair of holding members configured to hold the both end portions by inserting the both end portions thereinto, and a pair of stepped screws that passes through both end side portions of the headband spring in a plate thickness direction of the headband spring and that holds the headband spring movably in an axial direction of the pair of stepped screws with gaps between flange portions of the pair of stepped screws and the holding members.
    Type: Application
    Filed: May 26, 2022
    Publication date: December 1, 2022
    Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Naoya OKADA, Tetsuhiro AKIYOSHI
  • Publication number: 20220337532
    Abstract: A storage apparatus includes: a plurality of storage controllers including controller interfaces including a plurality of interface ports for connection to the plurality of switches having switch ports, a plurality of virtual networks configured by one of the switch ports is configured in the switch, and the storage controller sends a first packet for specifying the switch port to which the interface port is to be connected from the interface port to the plurality of virtual networks, and determines an address of the interface port used for data transfer between the storage controllers based on a switch number of the switch and a switch port number of the switch port in a case where a second packet including information for specifying the switch number of the switch and the switch port number of the switch port to which the interface port is to be connected is received.
    Type: Application
    Filed: August 31, 2021
    Publication date: October 20, 2022
    Inventors: Katsuya TANAKA, Naoya OKADA
  • Publication number: 20220308548
    Abstract: A differential logger stores, into a log storage from a device memory, a differential log being a log of a device value that has changed at each execution of a control program. A collective logger collectively stores, at a set time, collection target device values into the log storage as reference data to be used to collect the differential log. A split logger acquires as split logs, after the set time, logs of the device values multiple times, and stores the split logs into the reference data storage. The differential logger overwrites data in the log storage with the differential log after new reference data is stored into the log storage.
    Type: Application
    Filed: July 26, 2019
    Publication date: September 29, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Naoya OKADA, Takashi OKAMOTO
  • Patent number: 11366614
    Abstract: The storage system includes a controller and a storage drive accessible from the controller. The controller includes a memory and a processing unit. The memory includes a first cache area in which the writing of data by the storage drive is permitted, and a second cache area in which the writing of data by the storage drive is prohibited. A In the first cache area, the storage of data, by staging-in-advance in response to a read request for a sequential read, by the processing unit is permitted, and the storage of cache data in a dirty state by the processing unit is prohibited. In the second cache area, the storage of the cache data in the dirty state by the processing unit is permitted.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: June 21, 2022
    Assignee: Hitachi, Ltd.
    Inventors: Naoya Okada, Tomohiro Yoshihara, Sadahiro Sugimoto, Takashi Ochi, Jun Miyashita, Toshiya Seki
  • Patent number: 11342595
    Abstract: A power consumption control device includes: a storage battery; a heating unit; a storage unit storing a combination of a temperature of the storage battery and a remaining capacity of the storage battery in association with an increase amount in an effective capacity of the storage battery when the storage battery is heated by the heating unit which is supplied with each of the heating powers; a control unit configured to determine a first power which can be charged to the storage battery and to distribute the first power to the storage battery and the heating unit so that the increase amount in the effective capacity of the storage battery is maximized based on the first power, the increase amount for each of heating powers corresponding to the temperature of the storage battery and the remaining capacity of the storage battery, and the heating powers.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: May 24, 2022
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Toru Ogaki, Naoya Okada, Keisuke Fujimaki, Kodai Kasai
  • Patent number: 11256585
    Abstract: A storage system includes a first storage controller including a plurality of main storage media and one or more processor cores, and a second storage controller including a plurality of main storage media and one or more processor cores and performing communication with the first storage controller. Storage areas of the main storage media in the first storage controller are allocated to an address map. In response to the occurrence of failures in one or mode main storage media of the main storage media of the first storage controller, the first storage controller performs restarting to reallocate the storage areas of the main storage media excluding one or more main storage media having caused the failures to an address map reduced than before the occurrence of the failures. The second storage controller continues operating during the restarting of the first storage controller.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: February 22, 2022
    Assignee: HITACHI, LTD.
    Inventors: Yoshiaki Deguchi, Naoya Okada, Ryosuke Tatsumi, Kentaro Shimada, Sadahiro Sugimoto
  • Patent number: 11226769
    Abstract: In a large-scale storage system configured by combining a plurality of storage modules, it is possible to improve a read performance for deduplicated data. A large-scale storage system includes a first storage module and a second storage module each connected to a computing machine, the first storage module and the second storage module being connected to each other by a network, the first controller determines whether second data that is same as first data requested to be written is already stored in the second storage module when the first storage module receives a write request from the computing machine, and the first controller determines whether to store the first data in the first storage medium or to refer to the second data in the second storage module in a case in which the second data is already stored in the second storage module.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: January 18, 2022
    Assignee: HITACHI, LTD.
    Inventors: Nobumitsu Takaoka, Tomohiro Yoshihara, Naoya Okada
  • Patent number: 11200172
    Abstract: A storage system includes a plurality of controllers and a plurality of storage drives. A first cache area and a second cache area are set in a memory. The first cache area is permitted to be written data by the plurality of storage drives, and the second cache area is not permitted to be written data by the plurality of storage drives. In a case where the plurality of controllers duplicates data stored in the cache area to a cache area of another controller for redundancy, the plurality of controllers causes the data to be redundant in a second cache area of the other controller in a case where the data is stored in the first cache area, and causes the data to be redundant in a first cache area of the other controller in a case where the data is stored in the second cache area.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: December 14, 2021
    Assignee: HITACHI, LTD.
    Inventors: Naoya Okada, Tomohiro Yoshihara, Takashi Nagao, Ryosuke Tatsumi