Patents by Inventor Naoya Okamoto

Naoya Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160112689
    Abstract: A multi-projector system includes two or more projection devices including a first projection device and a second projection device, an image output device configured to output an image to each of the two or more projection devices, and an adjustment device configured to adjust projection positions of projection images on a medium to be projected, the projection images being projected by the two or more projection devices, and a first projection image emitted by the first projection device, and a second projection image emitted by the second projection device being projected on the medium to be projected to have an overlapped region.
    Type: Application
    Filed: December 28, 2015
    Publication date: April 21, 2016
    Inventor: Naoya Okamoto
  • Patent number: 9312350
    Abstract: A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor on a substrate, a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer, a gate trench formed in the second semiconductor layer or in the second and first semiconductor layers, a gate electrode formed at the gate trench, and a source electrode and a drain electrode formed on the second semiconductor layer. The gate trench has terminal parts of a bottom of the gate trench formed shallower than a center part of the bottom. A part of a sidewall of the gate trench is formed of a surface including an a-plane. The center part of the bottom is a c-plane. The terminal parts of the bottom form a slope from the c-plane to the a-plane.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: April 12, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Yuichi Minoura, Naoya Okamoto
  • Publication number: 20160099335
    Abstract: A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the first electrode and the second electrode; and connection parts electrically connected to the first electrode and the second electrode respectively, wherein a cavity is formed between the interlayer insulating film and a surface of the first electrode, a surface of the second electrode, and parts of surfaces of the connection parts.
    Type: Application
    Filed: December 11, 2015
    Publication date: April 7, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Shirou OZAKI, Naoya OKAMOTO, Kozo MAKIYAMA, Toshihiro OHKI
  • Patent number: 9306052
    Abstract: A compound semiconductor device includes: an electron transit layer; an electron supply layer over the electron transit layer; a gate electrode, a source electrode and a drain electrode at a level above the electron supply layer; and a porous electrical insulating film that covers the gate electrode, the source electrode and the drain electrode, the porous electrical insulating film containing an organic constituent, and a cavity being formed around the gate electrode in the porous electrical insulating film. A cross-linking layer is on a surface of the porous electrical insulating film at the cavity side.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: April 5, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Naoya Okamoto
  • Patent number: 9257514
    Abstract: A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the first electrode and the second electrode; and connection parts electrically connected to the first electrode and the second electrode respectively, wherein a cavity is formed between the interlayer insulating film and a surface of the first electrode, a surface of the second electrode, and parts of surfaces of the connection parts.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: February 9, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Naoya Okamoto, Kozo Makiyama, Toshihiro Ohki
  • Patent number: 9231056
    Abstract: A semiconductor device includes a drift layer having a structure wherein a plurality of quantum dot layers each including a quantum dot containing InxGa1-xN (0?x?1) and a burying layer burying the quantum dot and containing n-type Inx(GayAl1-y)1-xN (0?x?1, 0?y?1) are stacked.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: January 5, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Naoya Okamoto
  • Publication number: 20150360895
    Abstract: A support device for supporting a cylindrical member around which is wound an elongated body has: a support shaft for supporting the cylindrical member that is fitted to an external surface of the support shaft from an opening on one end in a longitudinal direction of the cylindrical member; an anchoring plates, built into the support shaft, for anchoring the cylindrical member from an inner circumferential side of the cylindrical member; and an operating means having an operation shaft of a smaller diameter than the support shaft, the operation shaft protruding forward from a distal end of the support shaft in order to operate the anchoring plates. Further, the support device has a protecting member which is attached to the distal end of the support shaft and through which is inserted the operation shaft. The protecting member further has a reduced-diameter section smaller in diameter than the support shaft.
    Type: Application
    Filed: June 5, 2013
    Publication date: December 17, 2015
    Applicant: LINTEC CORPORATION
    Inventors: Kaori Matsushita, Kazuhisa Yamaguchi, Kenichi Watanabe, Naoya Okamoto
  • Patent number: 9209042
    Abstract: A compound semiconductor device includes a compound semiconductor laminated structure, a passivation film formed on the compound semiconductor laminated structure and having a through-hole, and a gate electrode formed on the passivation film so as to plug the through-hole. A grain boundary between different crystalline orientations is formed in the gate electrode, and a starting point of the grain boundary is located apart from the through-hole on a flat surface of the passivation film.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: December 8, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Naoya Okamoto, Kozo Makiyama, Toshihiro Ohki, Yuichi Minoura, Shirou Ozaki, Toyoo Miyajima
  • Publication number: 20150333135
    Abstract: A compound semiconductor device includes: a compound semiconductor layer; a protective insulating film that covers a top of the compound semiconductor layer; and a gate electrode formed on the protective insulating film, wherein the protective insulating film has a first trench and a second trench which is formed side by side with the first trench and in which the protective insulating film remains with only a predetermined thickness on the compound semiconductor layer, and wherein the gate electrode fills the first trench, and one end of the gate electrode is away from the first trench and located at least in the second trench.
    Type: Application
    Filed: July 29, 2015
    Publication date: November 19, 2015
    Inventors: Kozo MAKIYAMA, Naoya Okamoto, Toshihide Kikkawa
  • Patent number: 9184272
    Abstract: A compound semiconductor device includes: a compound semiconductor layer; a protective insulating film that covers a top of the compound semiconductor layer; and a gate electrode formed on the protective insulating film, wherein the protective insulating film has a first trench and a second trench which is formed side by side with the first trench and in which the protective insulating film remains with only a predetermined thickness on the compound semiconductor layer, and wherein the gate electrode fills the first trench, and one end of the gate electrode is away from the first trench and located at least in the second trench.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: November 10, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Kozo Makiyama, Naoya Okamoto, Toshihide Kikkawa
  • Patent number: 9165530
    Abstract: A signal processor converts an input 3D image signal into a signal in which a left-eye signal and right-eye signal are rearranged temporally alternately. A driver of a liquid crystal display element includes a sub-frame data generator configuring all the sub-frames with step bit pulses and generating sub-frame data by using a drive gradation table in which the last sub-frame reaches a drive state when a drive gradation is “1” and the number of sub-frames reaching the drive state is increased one by one toward ahead of a sub-frame which has already reached the drive state, every time the drive gradation is increased by one. The liquid crystal display element is driven by the driver. An illumination optical system causes illumination light to enter into the liquid crystal display element. A projection lens projects modulated light emitted from the liquid crystal display element.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: October 20, 2015
    Assignee: JVC Kenwood Corporation
    Inventors: Naoya Okamoto, Hiroyuki Takada, Takeshi Makabe, Akihiro Sato
  • Publication number: 20150295074
    Abstract: A compound semiconductor device includes: an electron transit layer; an electron supply layer over the electron transit layer; a gate electrode, a source electrode and a drain electrode at a level above the electron supply layer; and a porous electrical insulating film that covers the gate electrode, the source electrode and the drain electrode, the porous electrical insulating film containing an organic constituent, and a cavity being formed around the gate electrode in the porous electrical insulating film. A cross-linking layer is on a surface of the porous electrical insulating film at the cavity side.
    Type: Application
    Filed: March 27, 2015
    Publication date: October 15, 2015
    Inventors: Shirou OZAKI, Naoya OKAMOTO
  • Patent number: 9117891
    Abstract: A compound semiconductor device includes: an electron transit layer formed of a compound semiconductor; and an electrode formed so as to overlie the electron transit layer with an insulating film interposed between the electron transit layer and the electrode, wherein part of the electron transit layer below the electrode are formed such that a first compound semiconductor having a first polar face and a second compound semiconductor having a second polar face are alternately arranged, and polarization charges in the first polar face have opposite polarity to polarization charges in the second polar face.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: August 25, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Lei Zhu, Naoya Okamoto
  • Publication number: 20150194512
    Abstract: A semiconductor device includes: a first semiconductor layer which is formed over a substrate and is formed from a nitride semiconductor; a second semiconductor layer which is formed over the first semiconductor layer and is formed from a nitride semiconductor; a third semiconductor layer which is formed over the second semiconductor layer and is formed from a nitride semiconductor; a source electrode and a drain electrode which are formed over the third semiconductor layer; an opening which is formed in the second semiconductor layer and the third semiconductor layer between the source electrode and the drain electrode; an insulating layer which is formed on a side surface and a bottom surface of the opening; and a gate electrode which is formed in the opening through the insulating layer.
    Type: Application
    Filed: December 4, 2014
    Publication date: July 9, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Toshihiro Ohki, LEI ZHU, NAOYA OKAMOTO, Yuichi Minoura, Shirou OZAKI
  • Patent number: 9035414
    Abstract: A semiconductor device includes a semiconductor layer and a Schottky electrode, a Schottky junction being formed between the semiconductor layer and the Schottky electrode. The Schottky electrode includes a metal part containing a metal, a Schottky junction being formed between the semiconductor layer and the metal part; and a nitride part around the metal part, the nitride part containing a nitride of the metal, and a Schottky junction being formed between the semiconductor layer and the nitride part.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: May 19, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Yuichi Minoura, Naoya Okamoto
  • Patent number: 9035353
    Abstract: A HEMT has a compound semiconductor layer, a protection film which has an opening and covers an upper side of the compound semiconductor layer, and a gate electrode which fills the opening and has a shape riding on the compound semiconductor layer, wherein the protection film has a stacked structure of a lower insulating film not containing oxygen and an upper insulating film containing oxygen, and the opening includes a first opening formed in the lower insulating film and a second opening formed in the upper insulating film and wider than the first opening, the first opening and the second opening communicating with each other.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: May 19, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Toshihiro Ohki, Naoya Okamoto, Yuichi Minoura, Kozo Makiyama, Shirou Ozaki
  • Patent number: 9035357
    Abstract: An HEMT includes, on an SiC substrate, a compound semiconductor layer, a silicon nitride (SiN) protective film having an opening and covering the compound semiconductor layer, and a gate electrode formed on the compound semiconductor layer so as to plug the opening. In the protective film, a projecting portion projecting from a side surface of the opening is formed at a lower layer portion 6a.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: May 19, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Kozo Makiyama, Naoya Okamoto, Toshihiro Ohki, Yuichi Minoura, Shirou Ozaki, Toyoo Miyajima
  • Publication number: 20150115411
    Abstract: A method of producing a semiconductor device includes forming an insulating film on a substrate on which a semiconductor layer is formed; removing a part of the insulating film by etching to form an opening in the insulating film; supplying steam with a temperature greater than or equal to 200° C. and less than or equal to 600° C. to the opening formed in the insulating film; after supplying the steam, applying a solution including a silicon compound to a side surface or the insulating film defining the opening; and forming a hydrophobic film on the side surface of the insulating film defining the opening by polymerizing the silicon compound.
    Type: Application
    Filed: October 14, 2014
    Publication date: April 30, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Shirou OZAKI, NAOYA OKAMOTO
  • Patent number: 8977716
    Abstract: The present invention relates to an information processing device, an information processing method, and a program for easily acquiring information. A television receiver accesses an application server and acquires an application list therefrom. When an application is selected from the application list, the television receiver again accesses the application server and acquires the selected application therefrom. While executing a process based on the acquired application, the television receiver accesses a content server as needed and acquires content data therefrom. The acquired application and content data are deleted from a storage unit when an end of the process based on the application is designated. The present invention applies to television receivers which acquire data via a network.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: March 10, 2015
    Assignee: Sony Corporation
    Inventors: Naoya Okamoto, Ken Onogi, Fujio Nobori, Seiichi Aoyagi
  • Patent number: 8969919
    Abstract: A field-effect transistor includes a carrier transport layer made of nitride semiconductor, a gate electrode having first and second sidewall surfaces on first and second sides, respectively, an insulating film formed directly on the gate electrode to cover at least one of the first and second sidewall surfaces, first and second ohmic electrodes formed on the first and second sides, respectively, a passivation film including a first portion extending from the first ohmic electrode toward the gate electrode to cover a surface area between the first ohmic electrode and the gate electrode and a second portion extending from the second ohmic electrode toward the gate electrode to cover a surface area between the second ohmic electrode and the gate electrode, wherein the insulating film is in direct contact with at least the first and second passivation film portions, and has a composition different from that of the passivation film.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: March 3, 2015
    Assignee: Fujitsu Limited
    Inventors: Toshihiro Ohki, Naoya Okamoto