Patents by Inventor Naoya Ota

Naoya Ota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11921518
    Abstract: A vehicle control system includes: a vehicle including an operation device; a first communication device; and a second communication device. In a case in which the first communication device is positioned in a first area containing a position of the vehicle, the vehicle operates in an operation waiting state in which the operation device is allowed to receive an operation. In a case in which the second communication device is positioned in a second area contained in the first area and smaller than the first area, the vehicle operates in the operation waiting state. In a case in which the first communication device is positioned in the first area and the second communication device is positioned in the second area, the second communication device generates a notification indicating that the vehicle is in the operation waiting state.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: March 5, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Jun Fujiyama, Naoya Koike, Jun Ogawa, Shinya Ota
  • Patent number: 11821795
    Abstract: A semiconductor device according to an embodiment includes a holding circuit including a buffer configured to obtain a heat stress information having a temperature dependency every predetermined period and a stress counter configured to accumulate the heat stress information and hold the accumulated value as a cumulative stress count value, a control circuit including an operation determination threshold value, and a wireless communication circuit. According to the semiconductor device according to the embodiment, while reducing the power consumption, it is possible to wirelessly transmit the cumulative heat stress information.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: November 21, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kan Takeuchi, Yoshio Takazawa, Fumio Tsuchiya, Daisuke Oshida, Naoya Ota, Masaki Shimada, Shinya Konishi
  • Patent number: 11068330
    Abstract: The semiconductor device has a module having a predetermined function, an error information acquisition circuit for acquiring error information about an error occurring in the module, a stress acquisition circuit for acquiring a stress accumulated value as an accumulated value of stress applied to the semiconductor device, and an analysis data storage for storing analysis data as data for analyzing the state of the semiconductor device, the error information and the stress accumulated value at the time of occurrence of the error being associated with each other.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: July 20, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoya Ota, Kan Takeuchi, Fumio Tsuchiya, Masaki Shimada, Shinya Konishi, Daisuke Oshida
  • Publication number: 20210080330
    Abstract: A semiconductor device according to an embodiment includes a holding circuit including a buffer configured to obtain a heat stress information having a temperature dependency every predetermined period and a stress counter configured to accumulate the heat stress information and hold the accumulated value as a cumulative stress count value, a control circuit including an operation determination threshold value, and a wireless communication circuit. According to the semiconductor device according to the embodiment, while reducing the power consumption, it is possible to wirelessly transmit the cumulative heat stress information.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 18, 2021
    Inventors: Kan TAKEUCHI, Yoshio TAKAZAWA, Fumio TSUCHIYA, Daisuke OSHIDA, Naoya OTA, Masaki SHIMADA, Shinya KONISHI
  • Publication number: 20200081757
    Abstract: The semiconductor device has a module having a predetermined function, an error information acquisition circuit for acquiring error information about an error occurring in the module, a stress acquisition circuit for acquiring a stress accumulated value as an accumulated value of stress applied to the semiconductor device, and an analysis data storage for storing analysis data as data for analyzing the state of the semiconductor device, the error information and the stress accumulated value at the time of occurrence of the error being associated with each other.
    Type: Application
    Filed: August 16, 2019
    Publication date: March 12, 2020
    Inventors: Naoya OTA, Kan TAKEUCHI, Fumio TSUCHIYA, Masaki SHIMADA, Shinya KONISHI, Daisuke OSHIDA
  • Publication number: 20130013153
    Abstract: The present invention provides a method in which a counting source is provided in data after analog/digital conversion to lessen a load placed when new and old data after the conversion are compared to each other. A log function is prepared in an A/D conversion controlling circuit. The log function latches the output of a counter in a 12-bit digital/analog converter at the timing of outputting a pulse from a comparator to determine data written into a data register group. In the case where a setting item related to log output in an ADCR is set at 1, not only the output of the 12-bit digital/analog converter, but also the output of a timer counter of an MTU is latched as a log.
    Type: Application
    Filed: September 15, 2012
    Publication date: January 10, 2013
    Inventor: Naoya OTA
  • Patent number: 8301337
    Abstract: The present invention provides a method in which a counting source is provided in data after analog/digital conversion to lessen a load placed when new and old data after the conversion are compared to each other. A log function is prepared in an A/D conversion controlling circuit. The log function latches the output of a counter in a 12-bit digital/analog converter at the timing of outputting a pulse from a comparator to determine data written into a data register group. In the case where a setting item related to log output in an ADCR is set at 1, not only the output of the 12-bit digital/analog converter, but also the output of a timer counter of an MTU is latched as a log.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: October 30, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Naoya Ota
  • Publication number: 20120259514
    Abstract: The present invention provides a method in which a counting source is provided in data after analog/digital conversion to lessen a load placed when new and old data after the conversion are compared to each other. A log function is prepared in an A/D conversion controlling circuit. The log function latches the output of a counter in a 12-bit digital/analog converter at the timing of outputting a pulse from a comparator to determine data written into a data register group. In the case where a setting item related to log output in an ADCR is set at 1, not only the output of the 12-bit digital/analog converter, but also the output of a timer counter of an MTU is latched as a log.
    Type: Application
    Filed: June 21, 2012
    Publication date: October 11, 2012
    Applicant: Renesas Electronics Corporation
    Inventor: Naoya OTA
  • Publication number: 20110035092
    Abstract: The present invention provides a method in which a counting source is provided in data after analog/digital conversion to lessen a load placed when new and old data after the conversion are compared to each other. A log function is prepared in an A/D conversion controlling circuit. The log function latches the output of a counter in a 12-bit digital/analog converter at the timing of outputting a pulse from a comparator to determine data written into a data register group. In the case where a setting item related to log output in an ADCR is set at 1, not only the output of the 12-bit digital/analog converter, but also the output of a timer counter of an MTU is latched as a log.
    Type: Application
    Filed: August 6, 2010
    Publication date: February 10, 2011
    Inventor: Naoya OTA