Abstract: A manufacturing method of a solar cell module according to an embodiment of the present disclosure includes a laminating process. The laminating process includes bringing a stack of overlapped elements of a solar cell module into a chamber, setting the stack on a hot plate, and heating the stack while pressing the stack with a pressing member. In the laminating process, the temperature of the pressing member is controlled by maintaining at least an entire contact portion of the pressing member, which is to be in contact with the stack, in contact with the upper chamber or the hot plate, or out of contact with the upper chamber and the hot plate. The temperature control is performed in a stand-by state before the stack is brought into the chamber.

Abstract: A manufacturing step for a solar cell module according to an example of an embodiment includes a lamination step of heating a multilayer structure while pressurizing the multilayer structure with a pressing member, the multilayer structure having a structure in which a solar cell, a first substrate, a second substrate, a first encapsulant, and a second encapsulant, are superimposed. In the lamination step, the pressurization by the pressing member is stopped at a temperature at which the loss modulus of the first encapsulant is maintained at 103 Pa or more.

Abstract: A power feeding apparatus for solar cells has: a voltage regulator, i.e., a voltage adjusting unit; a relay, i.e., a switch unit; and a control unit. The voltage regulator executes voltage adjustment with respect to an input voltage, and outputs, to a power output terminal, a voltage adjusted to a previously set voltage or lower. The relay is provided on a bypass line that is connected between a power input terminal and the power output terminal without having the voltage regulator therebetween, and the relay performs switching such that the bypass line is connected or interrupted. In the cases where the input voltage is equal to or lower than the predetermined voltage, the control unit performs control such that the bypass line is connected by means of the relay, and the input voltage is outputted from the power output terminal.

Abstract: A method of manufacturing a solar cell including a crystalline semiconductor substrate, includes: etching or washing at least part of a first principal surface of the substrate by treatment with an aqueous alkaline solution; and depositing a p-type semiconductor layer containing boron on at least part of a second principal surface of the substrate before the treatment with the aqueous alkaline solution.

Abstract: A power feeding apparatus for solar cells has: a voltage regulator, i.e., a voltage adjusting unit; a relay, i.e., a switch unit; and a control unit. The voltage regulator executes voltage adjustment with respect to an input voltage, and outputs, to a power output terminal, a voltage adjusted to a previously set voltage or lower. The relay is provided on a bypass line that is connected between a power input terminal and the power output terminal without having the voltage regulator therebetween, and the relay performs switching such that the bypass line is connected or interrupted. In the cases where the input voltage is equal to or lower than the predetermined voltage, the control unit performs control such that the bypass line is connected by means of the relay, and the input voltage is outputted from the power output terminal.

Abstract: Disclosed is a solar cell that comprises a substrate made of a semiconductor material, a first amorphous semiconductor layer placed on one region of the substrate and being of one conductivity type, a second amorphous semiconductor layer placed on another region of the substrate and being of another conductivity type, a substantially intrinsic i-type amorphous semiconductor layer provided above the first amorphous semiconductor layer, a third amorphous semiconductor layer provided on the i-type amorphous semiconductor layer and being of the other conductivity type, a first crystalline semiconductor layer placed between the first amorphous semiconductor layer and the i-type amorphous semiconductor layer and being of the one conductivity type, and a second crystalline semiconductor layer placed between the first crystalline semiconductor layer and the i-type amorphous semiconductor layer and being of the other conductivity type.

Abstract: Disclosed is a solar cell that comprises a substrate made of a semiconductor material, a first amorphous semiconductor layer placed on one region of the substrate and being of one conductivity type, a second amorphous semiconductor layer placed on another region of the substrate and being of another conductivity type, a substantially intrinsic i-type amorphous semiconductor layer provided above the first amorphous semiconductor layer, a third amorphous semiconductor layer provided on the i-type amorphous semiconductor layer and being of the other conductivity type, a first crystalline semiconductor layer placed between the first amorphous semiconductor layer and the i-type amorphous semiconductor layer and being of the one conductivity type, and a second crystalline semiconductor layer placed between the first crystalline semiconductor layer and the i-type amorphous semiconductor layer and being of the other conductivity type.

Abstract: Disclosed is a solar cell that comprises a substrate made of a semiconductor material, a first amorphous semiconductor layer placed on one region of the substrate and being of one conductivity type, a substantially intrinsic i-type amorphous semiconductor layer provided to extend from another region of the substrate over onto the first amorphous semiconductor layer, a second amorphous semiconductor layer provided on the i-type amorphous semiconductor layer and being of another conductivity type, a first crystalline semiconductor layer placed between the first amorphous semiconductor layer and the i-type amorphous semiconductor layer and being of the one conductivity type, a second crystalline semiconductor layer placed between the first crystalline semiconductor layer and the i-type amorphous semiconductor layer and being of the other conductivity type, and a third amorphous semiconductor layer placed between the second crystalline semiconductor layer and the i-type amorphous semiconductor layer and being of

Abstract: A semiconductor device includes a substrate made of a semiconductor material, an n-type semiconductor layer arranged on a portion of one principal surface of the substrate, and a p-type semiconductor layer arranged on a portion of the one principal surface of the substrate, the portion not provided with the n-type semiconductor layer. The n-type semiconductor layer includes a portion located right above the p-type semiconductor layer.

Abstract: A method of manufacturing a solar cell including a crystalline semiconductor substrate, includes: etching or washing at least part of a first principal surface of the substrate by treatment with an aqueous alkaline solution; and depositing a p-type semiconductor layer containing boron on at least part of a second principal surface of the substrate before the treatment with the aqueous alkaline solution.

Abstract: In a thin film solar cell module, a photovoltaic layer and a sealing layer 16 are sequentially disposed on a transparent substrate 11, the photovoltaic layer formed by connecting in series multiple photovoltaic elements each formed by sequentially stacking a transparent conductive film 12, photovoltaic conversion layers, and a rear surface electrode 15. Meanwhile, in a region where the rear surface electrodes 15 of the photovoltaic elements adjacent to each other are electrically separated, a metal film 18 is provided on a surface of the transparent conductive film 12 at a side of the sealing layer 16.

Abstract: A display capable of inhibiting a transistor from an instable operation resulting from fluctuation of the potential of a shielding film and suppressing occurrence of a malfunction is provided. This display comprises a first region including a first transistor, a first shielding film provided on the first region, arranged on a region corresponding to the first transistor and supplied with a first potential, a second region including a second transistor and a second shielding film provided on the second region, arranged on a region corresponding to the second transistor and supplied with a second potential.

Abstract: A display capable of inhibiting a transistor from an instable operation resulting from fluctuation of the potential of a shielding film and suppressing occurrence of a malfunction is provided. This display comprises a first region including a first transistor, a first shielding film provided on the first region, arranged on a region corresponding to the first transistor and supplied with a first potential, a second region including a second transistor and a second shielding film provided on the second region, arranged on a region corresponding to the second transistor and supplied with a second potential.

Abstract: A method of fabricating a thin film transistor by setting the temperature of a heat treatment for crystallizing an active layer which is formed on a substrate at a level not deforming the substrate and activating an impurity layer in a heat treatment method different from that employed for the heat treatment, and a semiconductor device prepared by forming a heat absorption film, a semiconductor film, a gate insulating film, and a gate electrode on a substrate, the heat absorption film being provided within a region substantially corresponding to the semiconductor film.

Abstract: A layered structure of wire(s) comprising a wiring layer made of a low resistance metal containing aluminum, copper or silver; and an alloy layer made of an intermediate phase containing the low resistance metal and a refractory metal. The refractory metal is molybdenum. There is also formed a layered structure of wire(s) made of an aluminum alloy containing a lanthanoid, wherein a number average crystal grain size is 16.9 nm or more. Crystal grain size may be larger than a mean free path of electrons to provide a layered structure of wire(s) with a reduced resistance.

Abstract: Provided is a semiconductor device capable of improving the characteristics of a plurality of semiconductor elements formed on a substrate while uniformizing the characteristics. This semiconductor device comprises a substrate and a plurality of semiconductor elements, formed on the substrate, each including a semiconductor layer having a channel region with carriers flowing in a first direction. The semiconductor layer constituting each of the plurality of semiconductor elements has a twin plane, and the twin plane is formed to extend in such a second direction that the carriers flowing through the channel region hardly traverse the twin plane.

Abstract: A method of fabricating a semiconductor device capable of obtaining a high-density laser beam necessary for crystallizing a semiconductor layer or activating an impurity while miniaturizing a lens group provided on the outlet of an optical fiber member is provided. This method of fabricating a semiconductor device comprises steps of connecting a laser oscillator oscillating a near infrared laser beam and an irradiation optical system with each other through an optical fiber member having a single core part and heating a semiconductor layer by irradiating the near infrared laser beam from the irradiation optical system.

Abstract: A deposition mask capable of relaxing nonuniformity of the thickness of a deposit formed on a substrate and reducing the width of a non-opening part of a mask layer by reducing the thickness of the mask layer is obtained. This deposition mask comprises a mask layer formed by a single silicon thin film and a mask pattern, formed on the mask layer, including a mask opening having an opening width increased toward a deposition source. The mask layer formed by a silicon thin film can be reduced in thickness due to small deflection caused by its own weight. Thus, the width of the non-opening part of the mask layer can be reduced, whereby the width of a part formed with no deposit can be reduced.

Abstract: A method of fabricating a thin film transistor by setting the temperature of a heat treatment for crystallizing an active layer which is formed on a substrate at a level not deforming the substrate and activating an impurity layer in a heat treatment method different from that employed for the heat treatment, and a semiconductor device prepared by forming a heat absorption film, a semiconductor film, a gate insulating film, and a gate electrode on a substrate, the heat absorption film being provided within a region substantially corresponding to the semiconductor film.

Abstract: A method of fabricating a thin film transistor by setting the temperature of a heat treatment for crystallizing an active layer which is formed on a substrate at a level not deforming the substrate and activating an impurity layer in a heat treatment method different from that employed for the heat treatment, and a semiconductor device prepared by forming a heat absorption film, a semiconductor film, a gate insulating film, and a gate electrode on a substrate, the heat absorption film being provided within a region substantially corresponding to the semiconductor film.