Patents by Inventor Naoya Sunachi
Naoya Sunachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240392475Abstract: Provided is a GaAs wafer having suppressed carrier concentration and low dislocation density, as well as a large proportion of the area of a region with zero dislocation density to the GaAs wafer surface. The GaAs wafer has a silicon concentration of 1.0×1017 cm?3 or more and less than 1.1×1018 cm?3; an indium concentration of 3.0×1018 cm?3 or more and less than 3.0×1019 cm?3; a boron concentration of 2.5×1018 cm?3 or more; a carrier concentration of 1.0×1016 cm?3 or more and 4.0×1017 cm?3 or less; and a proportion of the area of a region with zero dislocation density to the wafer surface of 91.0% or more.Type: ApplicationFiled: September 22, 2022Publication date: November 28, 2024Applicant: DOWA Electronics Materials Co., Ltd.Inventors: Naoya SUNACHI, Ryuichi TOBA, Akira AKAISHI
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Publication number: 20230392291Abstract: Provided is a GaAs wafer that can suitably be used to produce LiDAR sensors in particular and a method of producing a GaAs ingot that can be used to obtain such a GaAs wafer. The GaAs wafer has a silicon concentration of 5.0×1017 cm?3 or more and less than 3.5×1018 cm?3, an indium concentration of 3.0×1017 cm?3 or more and less than 3.0×1019 cm?3, and a boron concentration of 1.0×1018 cm?3 or more. The average dislocation density of the GaAs wafer is 1500/cm2 or less.Type: ApplicationFiled: September 27, 2021Publication date: December 7, 2023Applicant: DOWA Electronics Materials Co., Ltd.Inventors: Naoya SUNACHI, Ryuichi TOBA, Akira AKAISHI
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Publication number: 20230243067Abstract: Provided is a GaAs ingot with which a GaAs wafer having a carrier concentration of 5.5×1017 cm?3 or less and low dislocation density with an average dislocation density of 500/cm2 or less can be obtained by adding a small amount of In with Si. A seed side end and a center portion of a straight body part of the GaAs ingot each have a silicon concentration of 2.0×1017 cm?3 or more and less than 1.5×1018 cm?3, an indium concentration of 1.0×1017cm?3 or more and less than 6.5×1018 cm?3, a carrier concentration of 5.5×1017 cm?3 or less, and an average dislocation density of 500/cm2 or less.Type: ApplicationFiled: June 7, 2021Publication date: August 3, 2023Applicant: DOWA Electronics Materials Co., Ltd.Inventors: Naoya SUNACHI, Ryuichi TOBA, Akira AKAISHI
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Publication number: 20200083062Abstract: An electronic part mounting substrate includes: a metal plate 10 (for mounting thereon electronic parts) of aluminum or an aluminum alloy having a substantially rectangular planar shape, one major surface of the metal plate 10 being surface-processed so as to have a surface roughness of not less than 0.2 micrometers; a plating film 20 of nickel or a nickel alloy formed on the one major surface of the metal plate 10; an electronic part 14 bonded to the plating film 20 by a silver bonding layer 12 (containing a sintered body of silver); a ceramic substrate having a substantially rectangular planar shape, one major surface of the ceramic substrate 16 being bonded to the other major surface of the metal plate 10; and a radiating metal plate (metal base plate) 18 bonded to the other major surface of the ceramic substrate 16.Type: ApplicationFiled: November 12, 2019Publication date: March 12, 2020Applicant: DOWA METALTECH CO., LTD.Inventors: Naoya Sunachi, Hideyo Osanai, Satoru Kurita
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Patent number: 10510557Abstract: An electronic part mounting substrate includes: a metal plate 10 (for mounting thereon electronic parts) of aluminum or an aluminum alloy having a substantially rectangular planar shape, one major surface of the metal plate 10 being surface-processed so as to have a surface roughness of not less than 0.2 micrometers; a plating film 20 of nickel or a nickel alloy formed on the one major surface of the metal plate 10; an electronic part 14 bonded to the plating film 20 by a silver bonding layer 12 (containing a sintered body of silver); a ceramic substrate 16 having a substantially rectangular planar shape, one major surface of the ceramic substrate 16 being bonded to the other major surface of the metal plate 10; and a radiating metal plate (metal base plate) 18 bonded to the other major surface of the ceramic substrate 16.Type: GrantFiled: November 22, 2013Date of Patent: December 17, 2019Assignee: DOWA METALTECH CO., LTD.Inventors: Naoya Sunachi, Hideyo Osanai, Satoru Kurita
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Patent number: 9831157Abstract: In a method for producing an electronic part mounting substrate wherein an electronic part 14 is mounted on one major surface (a surface to which the electronic part 14 is to be bonded) of the metal plate 10 of copper, or aluminum or the aluminum alloy (when a plating film 20 of copper is formed on the surface), the one major surface of the metal plate 10 (or the surface of the plating film 20 of copper) is surface-machined to be coarsened so as to have a surface roughness of not less than 0.4 ?m, and then, a silver paste is applied on the surface-machined major surface (or the surface-machined surface of the plating film 20 of copper) to arrange the electronic part 14 thereon to sinter silver in the silver paste to form a silver bonding layer 12 to bond the electronic part 14 to the one major surface of the metal plate 10 (or the surface of the plating film 20 of copper) with the silver bonding layer 12.Type: GrantFiled: September 2, 2014Date of Patent: November 28, 2017Assignee: Dowa Metaltech Co., Ltd.Inventors: Naoya Sunachi, Hideyo Osanai, Satoru Kurita
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Publication number: 20160211195Abstract: In a method for producing an electronic part mounting substrate wherein an electronic part 14 is mounted on one major surface (a surface to which the electronic part 14 is to be bonded) of the metal plate 10 of copper, or aluminum or the aluminum alloy (when a plating film 20 of copper is formed on the surface), the one major surface of the metal plate 10 (or the surface of the plating film 20 of copper) is surface-machined to be coarsened so as to have a surface roughness of not less than 0.4 ?m, and then, a silver paste is applied on the surface-machined major surface (or the surface-machined surface of the plating film 20 of copper) to arrange the electronic part 14 thereon to sinter silver in the silver paste to form a silver bonding layer 12 to bond the electronic part 14 to the one major surface of the metal plate 10 (or the surface of the plating film 20 of copper) with the silver bonding layer 12.Type: ApplicationFiled: September 2, 2014Publication date: July 21, 2016Applicant: DOWA METALTECH CO., LTD.Inventors: Naoya Sunachi, Hideyo Osanai, Satoru Kurita
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Publication number: 20140147695Abstract: An electronic part mounting substrate includes: a metal plate 10 (for mounting thereon electronic parts) of aluminum or an aluminum alloy having a substantially rectangular planar shape, one major surface of the metal plate 10 being surface-processed so as to have a surface roughness of not less than 0.2 micrometers; a plating film 20 of nickel or a nickel alloy formed on the one major surface of the metal plate 10; an electronic part 14 bonded to the plating film 20 by a silver bonding layer 12 (containing a sintered body of silver); a ceramic substrate having a substantially rectangular planar shape, one major surface of the ceramic substrate 16 being bonded to the other major surface of the metal plate 10; and a radiating metal plate (metal base plate) 18 bonded to the other major surface of the ceramic substrate 16.Type: ApplicationFiled: November 22, 2013Publication date: May 29, 2014Applicant: DOWA METALTECH CO., LTD.Inventors: Naoya Sunachi, Hideyo Osanai, Satoru Kurita
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Patent number: 7256476Abstract: There is provided a notched compound semiconductor crystal having the same specification even if it is turned over. With respect to a compound semiconductor wafer produced by slicing a compound semiconductor crystal having a crystal plane of (100) plane, the crystal is sliced so as to be tilted from the (100) plane in a direction of [101] or [10-1] when a notch is formed in a direction of [010], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [0-10] or [010] when a notch is formed in a direction of [001], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [001] or [00-1] when a notch is formed in a direction of [0-10] , or the crystal is sliced so as to be tilted from the (100) plane in a direction of [010] or [0-10] when a notch is formed in a direction of [00-1].Type: GrantFiled: November 7, 2005Date of Patent: August 14, 2007Assignee: Dowa Mining Co., Ltd.Inventors: Ryuichi Toba, Naoya Sunachi
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Patent number: 7256478Abstract: There is provided a notched compound semiconductor crystal having the same specification even if it is turned over. With respect to a compound semiconductor wafer produced by slicing a compound semiconductor crystal having a crystal plane of (100) plane, the crystal is sliced so as to be tilted from the (100) plane in a direction of [101] or [10-1] when a notch is formed in a direction of [010], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [0-10] or [010] when a notch is formed in a direction of [001], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [001] or [00-1] when a notch is formed in a direction of [0-10], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [010] or [0-10] when a notch is formed in a direction of [00-1].Type: GrantFiled: November 7, 2005Date of Patent: August 14, 2007Assignee: Dowa Mining Co., Ltd.Inventors: Ryuichi Toba, Naoya Sunachi
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Patent number: 7256477Abstract: There is provided a notched compound semiconductor crystal having the same specification even if it is turned over. With respect to a compound semiconductor wafer produced by slicing a compound semiconductor crystal having a crystal plane of (100) plane, the crystal is sliced so as to be tilted from the (100) plane in a direction of [101] or [10-1] when a notch is formed in a direction of [010], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [0-10] or [010] when a notch is formed in a direction of [001], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [001] or [00-1] when a notch is formed in a direction of [0-10], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [010] or [0-10] when a notch is formed in a direction of [00-1].Type: GrantFiled: November 7, 2005Date of Patent: August 14, 2007Assignee: Dowa Mining Co., Ltd.Inventors: Ryuichi Toba, Naoya Sunachi
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Patent number: 7211834Abstract: An improvement in electrode reliability is realized by preventing over-etching on a peripheral lower portion of an electrode while maintaining the flow of steps of roughening a surface after forming the electrode on a semiconductor substrate. After a P-side electrode 4 is formed on a main surface 3a of a semiconductor substrate 3, a surface of the P-side electrode 4 is selectively covered with a protective film 12, after the semiconductor substrate 3 is cut into chips, the surface is roughened from above the protective film 12, the main surface 3a around the P-side electrode 4 and a side surface are roughened with a non-chemical treatment region 10 which is a non-roughened surface region being left in a peripheral portion of the P-side electrode 4 covered with the protective film 12, and thereafter the protective film 12 is removed.Type: GrantFiled: March 30, 2004Date of Patent: May 1, 2007Assignee: Dowa Electronics Materials Co., Ltd.Inventors: Naoya Sunachi, Hiroyuki Matsuoka
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Publication number: 20060113559Abstract: There is provided a notched compound semiconductor crystal having the same specification even if it is turned over. With respect to a compound semiconductor wafer produced by slicing a compound semiconductor crystal having a crystal plane of (100) plane, the crystal is sliced so as to be tilted from the (100) plane in a direction of [101] or [10-1] when a notch is formed in a direction of [010], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [0-10] or [010] when a notch is formed in a direction of [001], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [001] or [00-1] when a notch is formed in a direction of [0-10], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [010] or [0-10] when a notch is formed in a direction of [00-1].Type: ApplicationFiled: November 7, 2005Publication date: June 1, 2006Inventors: Ryuichi Toba, Naoya Sunachi
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Publication number: 20060113558Abstract: There is provided a notched compound semiconductor crystal having the same specification even if it is turned over. With respect to a compound semiconductor wafer produced by slicing a compound semiconductor crystal having a crystal plane of (100) plane, the crystal is sliced so as to be tilted from the (100) plane in a direction of [101] or [10-1] when a notch is formed in a direction of [010], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [0-10] or [010] when a notch is formed in a direction of [001], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [001] or [00-1] when a notch is formed in a direction of [0-10], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [010] or [0-10] when a notch is formed in a direction of [00-1].Type: ApplicationFiled: November 7, 2005Publication date: June 1, 2006Inventors: Ryuichi Toba, Naoya Sunachi
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Publication number: 20060060883Abstract: There is provided a notched compound semiconductor crystal having the same specification even if it is turned over. With respect to a compound semiconductor wafer produced by slicing a compound semiconductor crystal having a crystal plane of (100) plane, the crystal is sliced so as to be tilted from the (100) plane in a direction of [101] or [10-1] when a notch is formed in a direction of [010], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [0-10] or [010] when a notch is formed in a direction of [001], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [001] or [00-1] when a notch is formed in a direction of [0-10] , or the crystal is sliced so as to be tilted from the (100) plane in a direction of [010] or [0-10] when a notch is formed in a direction of [00-1].Type: ApplicationFiled: November 7, 2005Publication date: March 23, 2006Inventors: Ryuichi Toba, Naoya Sunachi
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Patent number: 6998700Abstract: There is provided a notched compound semiconductor crystal having the same specification even if it is turned over. With respect to a compound semiconductor wafer produced by slicing a compound semiconductor crystal having a crystal plane of (100) plane, the crystal is sliced so as to be tilted from the (100) plane in a direction of [101] or [10?1] when a notch is formed in a direction of [010], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [0?10] or [010] when a notch is formed in a direction of [001], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [001] or [00?1] when a notch is formed in a direction of [0?10], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [010] or [0?10] when a notch is formed in a direction of [00?1].Type: GrantFiled: June 10, 2002Date of Patent: February 14, 2006Assignee: Dowa Mining Co., LTDInventors: Ryuichi Toba, Naoya Sunachi
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Publication number: 20060011934Abstract: An improvement in electrode reliability is realized by preventing over-etching on a peripheral lower portion of an electrode while maintaining the flow of steps of roughening a surface after forming the electrode on a semiconductor substrate. After a P-side electrode 4 is formed on a main surface 3a of a semiconductor substrate 3, a surface of the P-side electrode 4 is selectively covered with a protective film 12, after the semiconductor substrate 3 is cut into chips, the surface is roughened from above the protective film 12, the main surface 3a around the P-side electrode 4 and a side surface are roughened with a non-chemical treatment region 10 which is a non-roughened surface region being left in a peripheral portion of the P-side electrode 4 covered with the protective film 12, and thereafter the protective film 12 is removed.Type: ApplicationFiled: March 30, 2004Publication date: January 19, 2006Applicant: DOWA MINING CO., LTD.Inventors: Naoya Sunachi, Hiroyuki Matsuoka
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Publication number: 20040242001Abstract: There is provided a notched compound semiconductor crystal having the same specification even if it is turned over. With respect to a compound semiconductor wafer produced by slicing a compound semiconductor crystal having a crystal plane of (100) plane, the crystal is sliced so as to be tilted from the (100) plane in a direction of [101] or [10-1] when a notch is formed in a direction of [010], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [0-10] or [010] when a notch is formed in a direction of [001], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [001] or [00-1] when a notch is formed in a direction of [0-10], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [010] or [0-10] when a notch is formed in a direction of [00-1].Type: ApplicationFiled: March 12, 2004Publication date: December 2, 2004Inventors: Ryuichi Toba, Naoya Sunachi