Patents by Inventor Naoya Waki

Naoya Waki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8502712
    Abstract: According to one embodiment, an analogue to digital converter converts an analogue input signal to a digital output signal. The converter includes an analogue to digital converting unit, a multiplexer, a pseudo-alias signal generator, a gain controller, and an alias signal compensator. The analogue to digital converting unit converts the analogue input signal to a plurality of digital signals. The multiplexer sequentially selects one of the digital signals and outputs the selected digital signal as a multiplexer output. The pseudo-alias signal generator generates a plurality of pseudo-alias signals from the digital signals. The pseudo-alias signal simulates an alias signal component in the multiplexer output. The gain controller generates a plurality of gain control signals by using the pseudo-alias signals. The gain control signal controls gain of the digital output signal. The alias signal compensator compensates the alias signal component by using the gain control signals.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: August 6, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoya Waki, Junya Matsuno, Takafumi Yamaji, Masanori Furuta
  • Publication number: 20130076544
    Abstract: According to one embodiment, an analogue to digital converter converts an analogue input signal to a digital output signal. The converter includes an analogue to digital converting unit, a multiplexer, a pseudo-alias signal generator, a gain controller, and an alias signal compensator. The analogue to digital converting unit converts the analogue input signal to a plurality of digital signals. The multiplexer sequentially selects one of the digital signals and outputs the selected digital signal as a multiplexer output. The pseudo-alias signal generator generates a plurality of pseudo-alias signals from the digital signals. The pseudo-alias signal simulates an alias signal component in the multiplexer output. The gain controller generates a plurality of gain control signals by using the pseudo-alias signals. The gain control signal controls gain of the digital output signal. The alias signal compensator compensates the alias signal component by using the gain control signals.
    Type: Application
    Filed: March 20, 2012
    Publication date: March 28, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Naoya Waki, Junya Matsuno, Takafumi Yamaji, Masanori Furuta
  • Patent number: 8004435
    Abstract: To reduce a random noise power included in an analog input signal, a discrete-time circuit samples an inputted analog signal a plurality of number of times at different times respectively and performs averaging processing on sampling results, thus enabling to respond appropriately even if an input signal has a high frequency without increasing a size of the circuit.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: August 23, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoya Waki, Hirotomo Ishii
  • Publication number: 20100207795
    Abstract: To reduce a random noise power included in an analog input signal, a discrete-time circuit samples an inputted analog signal a plurality of number of times at different times respectively and performs averaging processing on sampling results, thus enabling to respond appropriately even if an input signal has a high frequency without increasing a size of the circuit.
    Type: Application
    Filed: November 5, 2009
    Publication date: August 19, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Naoya Waki, Hirotomo Ishii