Abstract: According to one embodiment, a semiconductor circuit includes a first transimpedance amplifier and a second transimpedance amplifier. The first transimpedance amplifier is configured to convert an input current to a first output voltage and output the first output voltage from a first output terminal when a reference voltage is supplied to a first input terminal and the input current is supplied to a second input terminal. The second transimpedance amplifier has a circuit configuration similar to a circuit configuration of the first transimpedance amplifier. The second transimpedance amplifier is configured to output a second output voltage from a second output terminal when the reference voltage is supplied to a third input terminal.

Abstract: According to one embodiment, a semiconductor integrated circuit 1 includes a sample and hold circuit and a clock generation circuit. The sample and hold circuit has a device with a first withstand voltage and a device with a second withstand voltage that is higher than the first withstand voltage. The clock generation circuit generates a first clock signal to be supplied to the first withstand voltage device and generates a second clock signal to be supplied to the second withstand voltage device based on the first clock signal. The clock generation circuit has a delay adjustment circuit that performs adjustment to delay the second clock signal and bring a phase of the second clock signal close to a phase of the first clock signal in the generation of the second clock signal.

Abstract: According to one embodiment, a semiconductor integrated circuit 1 includes a sample and hold circuit and a clock generation circuit. The sample and hold circuit has a device with a first withstand voltage and a device with a second withstand voltage that is higher than the first withstand voltage. The clock generation circuit generates a first clock signal to be supplied to the first withstand voltage device and generates a second clock signal to be supplied to the second withstand voltage device based on the first clock signal. The clock generation circuit has a delay adjustment circuit that performs adjustment to delay the second clock signal and bring a phase of the second clock signal close to a phase of the first clock signal in the generation of the second clock signal.

Abstract: According to an embodiment, a sample-hold circuit according to this embodiment is made up of a first device having a first withstand voltage and a second device having a second withstand voltage lower than the first withstand voltage. The sample-hold circuit includes a first switch element, a first capacitor, a second switch element, a third switch element, and a fourth switch element. The first switch element has the first withstand voltage. The first switch element operates upon receiving a first signal output from the device having the first withstand voltage. The second switch element has the first withstand voltage. The third switch element has the second withstand voltage. The fourth switch element has the second withstand voltage.

Abstract: According to an embodiment, a sample-hold circuit according to this embodiment is made up of a first device having a first withstand voltage and a second device having a second withstand voltage lower than the first withstand voltage. The sample-hold circuit includes a first switch element, a first capacitor, a second switch element, a third switch element, and a fourth switch element. The first switch element has the first withstand voltage. The first switch element operates upon receiving a first signal output from the device having the first withstand voltage. The second switch element has the first withstand voltage. The third switch element has the second withstand voltage. The fourth switch element has the second withstand voltage.

Abstract: According to one embodiment, an analogue to digital converter converts an analogue input signal to a digital output signal. The converter includes an analogue to digital converting unit, a multiplexer, a pseudo-alias signal generator, a gain controller, and an alias signal compensator. The analogue to digital converting unit converts the analogue input signal to a plurality of digital signals. The multiplexer sequentially selects one of the digital signals and outputs the selected digital signal as a multiplexer output. The pseudo-alias signal generator generates a plurality of pseudo-alias signals from the digital signals. The pseudo-alias signal simulates an alias signal component in the multiplexer output. The gain controller generates a plurality of gain control signals by using the pseudo-alias signals. The gain control signal controls gain of the digital output signal. The alias signal compensator compensates the alias signal component by using the gain control signals.

Abstract: According to one embodiment, an analogue to digital converter converts an analogue input signal to a digital output signal. The converter includes an analogue to digital converting unit, a multiplexer, a pseudo-alias signal generator, a gain controller, and an alias signal compensator. The analogue to digital converting unit converts the analogue input signal to a plurality of digital signals. The multiplexer sequentially selects one of the digital signals and outputs the selected digital signal as a multiplexer output. The pseudo-alias signal generator generates a plurality of pseudo-alias signals from the digital signals. The pseudo-alias signal simulates an alias signal component in the multiplexer output. The gain controller generates a plurality of gain control signals by using the pseudo-alias signals. The gain control signal controls gain of the digital output signal. The alias signal compensator compensates the alias signal component by using the gain control signals.

Abstract: To reduce a random noise power included in an analog input signal, a discrete-time circuit samples an inputted analog signal a plurality of number of times at different times respectively and performs averaging processing on sampling results, thus enabling to respond appropriately even if an input signal has a high frequency without increasing a size of the circuit.

Abstract: To reduce a random noise power included in an analog input signal, a discrete-time circuit samples an inputted analog signal a plurality of number of times at different times respectively and performs averaging processing on sampling results, thus enabling to respond appropriately even if an input signal has a high frequency without increasing a size of the circuit.