Abstract: A switched power converter and a method are presented. The converter has a main stage with a main converter that exhibits an inductor and at least one switch to control an inductor current through the inductor. Furthermore, the switched power converter has an auxiliary stage to determine a sensed current indicative of the inductor current, and to provide or sink an auxiliary current to or from the output node, wherein the auxiliary current depends on the sensed current. In addition, the switched power converter has control circuitry to determine whether the output voltage falls below an undershoot threshold or exceeds an overshoot threshold, and to activate the auxiliary stage to provide or sink the auxiliary current, if it is determined that the output voltage falls below the undershoot threshold or exceeds the overshoot threshold.

Abstract: A voltage proportional to a pulse width modulation (PWM) duty cycle is generated, using a low pass filter (LPF). A 2nd or higher order LPF is provided, giving a 90×(2n+1) degree phase shift for (n=0, 1, 2, . . . ), so that the sampling timing at the latter stages can be at the rising and/or falling edge of the PWM input signal. A switched capacitor circuit after the 2nd or higher order LPF is provided, removing a voltage ripple on an LPF output, and using a smaller device area.

Abstract: A switching converter and a method for providing an output voltage is presented. The switching converter includes an inductor coupled to a pair of power switches, a signal generator and a controller. The first power switch is used to magnetize the inductor, while the second power switch is used to de-magnetize it. The signal generator is adapted to generate a modulated signal having a pulse width variable between a minimum value and a maximum value and to drive the first and second power switches based on the modulated signal. Upon identifying that the modulated signal has the minimum pulse width value, the controller increases a reverse current flowing from the inductor through the second power switch to prevent the output voltage from increasing above a target value.

Abstract: The present disclosure relates to methods and circuits to achieve a buck-boost switching regulator that allows changing operation modes without causing large output ripples during transition of operation modes Increased error amplifier output voltage range over which the converter stays in its present operating mode (buck or boost or buck-boost), resulting in hysteresis between error amplifier output voltage and output voltage). The larger the hysteresis, the smaller will be the likeliness of having to switch between modes. A first embodiment is combining masking logic applied to signals driving the switches of the switching regulator and offset feedback to outputs of the error amplifier in order to providing hysteresis to suppress operation mode bounce and to minimize ripples while a second embodiment is monitoring pulse width of PWM pulses by a pulse width checker.

Abstract: A transient response circuit provides faster transient response time of an electronic device so that less overshoot or undershoot of an output signal of the electronic device occurs when a large load and/or line transient signal is present at an input and/or output terminal of the electronic device. The transient response circuit has a transient detection circuit and an assist circuit. The transient detection circuit monitors a feedback signal applied to an input terminal of the control stage, and generates transient detection signals indicating that detection of a large load and/or line transient signal has occurred. The assist circuit communicates receives the transient detection signal and charges or discharges a loop filter capacitor of the control stage for causing the control stage to regulate the output signal to decrease overshoot or undershoot upon receipt of the transient detection signal.

Abstract: The disclosure describes decreasing the overshoot and undershoots during the mode transitions of a Buck-Boost switching converter, without causing mode bounces. This is achieved by a main compensation capacitor of an error amplifier being charged or discharged, so that the output voltage level is shifted close to the target value. The expected behavior of the disclosure is contributed to two items, one is a mode transition detector, configured to detect mode transition among buck, buck-boost, boost, and ½f buck/boost modes, and the other is charge/discharge circuitry configured within one-clock cycle of a mode transition being detected.

Abstract: The disclosure describes decreasing the overshoot and undershoots during the mode transitions of a Buck-Boost switching converter, without causing mode bounces. This is achieved by a main compensation capacitor of an error amplifier being charged or discharged, so that the output voltage level is shifted close to the target value. The expected behavior of the disclosure is contributed to two items, one is a mode transition detector, configured to detect mode transition among buck, buck-boost, boost, and Y2f buck/boost modes, and the other is charge/discharge circuitry configured within one-clock cycle of a mode transition being detected.

Abstract: A circuit configured for improving the large signal response of a control stage circuit of a switch mode DC/DC power converter by increasing the differential input range of an error amplifier by segmenting and adding an offset to the error amplifier input and output. When a transient is detected, the feedback voltage is offset in multiple segments by multiple offset voltage sources to prevent saturation of the control stage circuit. Counteracting offset voltages are added to an output of an error amplifier to prevent overshoot or undershoot. A feed-forward compensation signal is generated with the amplitude of the signal being clamped to fixed voltage levels between a minimum and a maximum amplitude of the feed-forward compensation signal. The feed-forward compensation signal is added to the output of the error amplifier to produce an output error signal of the control stage circuit configured for controlling the modulating of the switch mode DC/DC power converter.

Abstract: A circuit configured for improving the large signal response of a control stage circuit of a switch mode DC/DC power converter by increasing the differential input range of an error amplifier by segmenting and adding an offset to the error amplifier input and output. When a transient is detected, the feedback voltage is offset in multiple segments by multiple offset voltage sources to prevent saturation of the control stage circuit. Counteracting offset voltages are added to an output of an error amplifier to prevent overshoot or undershoot. A feed-forward compensation signal is generated with the amplitude of the signal being clamped to fixed voltage levels between a minimum and a maximum amplitude of the feed-forward compensation signal. The feed-forward compensation signal is added to the output of the error amplifier to produce an output error signal of the control stage circuit configured for controlling the modulating of the switch mode DC/DC power converter.

Abstract: Circuits and methods control output voltage overshoot and undershoot of an SMPC in response to a load current transient. The SMPC control stage has at least one load variation detector that compares a feedback signal with at least one transient threshold level to determine that occurrence of the load current transient. When the load current transient has occurred, the at least one load variation detector causes a switch stage to be turned on to source or sink current to or from the load circuit to compensate the load current transient. A slope detector determines a change in polarity of the slope of the load current transient. When the slope changes polarity, the slope detector sends a signal for preventing an overshoot or an undershoot of the output voltage of the SMPC once the load current transient has been compensated.

Abstract: A transient response circuit provides faster transient response time of an electronic device so that less overshoot or undershoot of an output signal of the electronic device occurs when a large load and/or line transient signal is present at an input and/or output terminal of the electronic device. The transient response circuit has a transient detection circuit and an assist circuit. The transient detection circuit monitors a feedback signal applied to an input terminal of the control stage, and generates transient detection signals indicating that detection of a large load and/or line transient signal has occurred. The assist circuit communicates receives the transient detection signal and charges or discharges a loop filter capacitor of the control stage for causing the control stage to regulate the output signal to decrease overshoot or undershoot upon receipt of the transient detection signal.

Abstract: A circuit and method for a level shift circuit with increased flexibility is described. The level shifting circuit includes an NMOS pair, a PMOS pair cross-coupled to the NMOS pair, an auxiliary transient response network parallel to the PMOS pair configured to provide a parallel current path, and a delay network configured to provide a delay to the auxiliary transient response network. Additionally, a method of providing a level shift circuit includes the steps of (a) providing an NMOS pair, (b) cross-coupling the NMOS pair to a PMOS pair, connected in parallel with an auxiliary transient response network which includes a pair of cascode PMOS, and a step (c) of providing a pair of delay inverters at inputs to the auxiliary transient response network.

Abstract: A switching DC-to-DC converter has an adaptive duty cycle limiting circuit with an inductor current sensor to generate a sense signal indicative of magnitude of the inductor current. A replica signal is generated from the sense signal and transferred through a replica parasitic resistance circuit. A differential voltage is developed across the replica parasitic resistances and compared with a maximum limit voltage level. The maximum limit voltage level is indicates that a gain level of the switching DC-to-DC converter has decreased even though the duty cycle has increased. A duty cycle limit signal is generated and transferred to disable a switch in a switching circuit for limiting the duty cycle of the switching DC-to-DC converter, when the gain level has decreased such that the switching DC-to-DC converter does not enter a region where the gain of the switching DC-to-DC converter has a negative slope.

Abstract: An adaptive duty cycle limiting circuit is used with a switching DC-to-DC converter for preventing the duty cycle entering a region of operation having negative gain. The adaptive duty cycle limiting circuit includes a duty cycle ramp signal generator, a voltage source for providing a voltage having a fractional value of an input voltage source, and a comparator that compares the duty cycle ramp signal with the fractional value of the input voltage source. When the voltage level of the duty cycle ramp signal is less than the fractional value of the voltage source, a cycle limit signal is activated and communicated to a switching control circuit to adjust the duty cycle of the switching DC-to-DC converter to prevent the duty cycle entering the region of operation where the gain of the switching DC-to-DC converter becomes negative.

Abstract: An adaptive duty cycle limiting circuit is used with a switching DC-to-DC converter for preventing the duty cycle entering a region of operation having negative gain. The adaptive duty cycle limiting circuit includes a duty cycle ramp signal generator, a voltage source for providing a voltage having a fractional value of an input voltage source, and a comparator that compares the duty cycle ramp signal with the fractional value of the input voltage source. When the voltage level of the duty cycle ramp signal is less than the fractional value of the voltage source, a cycle limit signal is activated and communicated to a switching control circuit to adjust the duty cycle of the switching DC-to-DC converter to prevent the duty cycle entering the region of operation where the gain of the switching DC-to-DC converter becomes negative.

Abstract: A switching DC-to-DC converter has an adaptive duty cycle limiting circuit with an inductor current sensor to generate a sense signal indicative of magnitude of the inductor current. A replica signal is generated from the sense signal and transferred through a replica parasitic resistance circuit. A differential voltage is developed across the replica parasitic resistances and compared with a maximum limit voltage level. The maximum limit voltage level is indicates that a gain level of the switching DC-to-DC converter has decreased even though the duty cycle has increased. A duty cycle limit signal is generated and transferred to disable a switch in a switching circuit for limiting the duty cycle of the switching DC-to-DC converter, when the gain level has decreased such that the switching DC-to-DC converter does not enter a region where the gain of the switching DC-to-DC converter has a negative slope.

Abstract: The present disclosure relates to methods and circuits to achieve a buck-boost switching regulator that allows changing operation modes without causing large output ripples during transition of operation modes Increased error amplifier output voltage range over which the converter stays in its present operating mode (buck or boost or buck-boost), resulting in hysteresis between error amplifier output voltage and output voltage). The larger the hysteresis, the smaller will be the likeliness of having to switch between modes. A first embodiment is combining masking logic applied to signals driving the switches of the switching regulator and offset feedback to outputs of the error amplifier in order to providing hysteresis to suppress operation mode bounce and to minimize ripples while a second embodiment is monitoring pulse width of PWM pulses by a pulse width checker.

Abstract: Enzyme composition having the activities of cellulase laminarinase, xylanase, dextranase, amilase, pectinase and protease which is obtained by culturing Basidiomycetes belonging to the genus Irpex is used for promoting secretion of milk of livestock and improving the quality of the milk.