Abstract: An in-vivo camera device and an in-vivo monitoring camera system more excellent in usability are proposed. An in-vivo camera device includes a camera unit introduced into a body, a support member, and a camera-side cable. The support member has a trocar connection portion for connection with a trocar at a front end side, and is connected to the trocar in a state in which the trocar connection portion is fitted into the trocar by applying tensile force to the camera-side cable passing through the trocar. The support member is provided with a guide introduction portion that is formed to be relatively long at the front end side as a stabilization structure for stabilizing connection with the trocar.

Abstract: A manufacturing method includes: a step of forming a light-emitting element layer by forming a semiconductor layer, a light-emitting layer, and a semiconductor layer in this order from a side with a first substrate on a surface, of the first substrate, on one side; a step of forming a separation trench in the light-emitting element layer to form a plurality of island shape light-emitting element layers; a step of forming a light shielding layer made of a material different from a material of the light-emitting element layer, in the separation trench; and a step of forming a plurality of light-emitting elements each including a corresponding one of the plurality of island shape light-emitting element layers having a height less than a height of the light shielding layer by etching a portion of the semiconductor layers of each of the plurality of island shape light-emitting element layers.

Abstract: An in-vivo camera device and an in-vivo monitoring camera system more excellent in usability are proposed. An in-vivo camera device includes a camera unit introduced into a body, a support member, and a camera-side cable. The support member has a trocar connection portion for connection with a trocar at a front end side, and is connected to the trocar in a state in which the trocar connection portion is fitted into the trocar by applying tensile force to the camera-side cable passing through the trocar. The support member is provided with a guide introduction portion that is formed to be relatively long at the front end side as a stabilization structure for stabilizing connection with the trocar.

Abstract: A socket electrically connectable with a pin inserted thereinto includes a pressed portion, which is pressed by the pin, and clamp pieces, which are deformed, in response to the pressed portion being pressed, into a clamp position, in which the clamp pieces clamp the pin therebetween, from an insertion position, in which the clamp pieces allow the pin to be inserted thereinto.

Abstract: An in-vivo imaging device includes a camera, a support rod insertable into a tubular instrument, and a gripping portion disposed at an end portion of the support rod for gripping the camera. When the support rod is pulled up outward of a body, the gripping portion is deformed and grips the camera by coming into contact with an in-vivo side end portion of the tubular instrument.

Abstract: An inspection method for a touch panel control substrate, with which inspection for mounting failure is able to be simply executed, is provided. On the basis of a response that is obtained, in response to a drive signal supplied to a first drive line terminal (101E), in a different drive line terminal (102E, 103E), an electrical connection state between the first drive line terminal (101E) and the drive line terminal (102E, 103E) is detected.

Abstract: The present invention provides a touch panel controller for controlling even a large touch panel with little EMI. The touch panel controller of the present invention includes a plurality of driving circuits (DC1 through DCm) for driving respective drive lines (DL1 through DLm) of a capacitive touch panel unit 2 by supplying driving signals (Ds) to the respective drive lines (DL1 through DLm), and a rise/fall time of each of the driving signals (Ds) is variable.

Abstract: The present invention provides a touch panel controller for controlling even a large touch panel with little EMI. The touch panel controller of the present invention includes a plurality of driving circuits (DC1 through DCm) for driving respective drive lines (DL1 through DLm) of a capacitive touch panel unit 2 by supplying driving signals (Ds) to the respective drive lines (DL1 through DLm), and a rise/fall time of each of the driving signals (Ds) is variable.

Abstract: In one embodiment of the present invention, an electrostatic discharge withstand voltage evaluating device includes: an application device, including a first connecting section and a second connecting section, for supplying pulse electric charge, the first connecting section being connectable to one or whole terminal (s) of one of input terminals and output terminals of a source driver, and supplying electric charge to the source driver, the second connecting section being connectable to one or whole terminal(s) of the other one of the input terminals and the output terminals, and enabling said one or whole terminal(s) of the other one of the input terminals and the output terminals to be grounded; and a common connecting section being connectable to the plurality of output terminals of the source driver, and causing the plurality of output terminals to be electrically connected to each other, wherein the output terminals of the source driver are connected, via the common connecting section, to one of the fir

Abstract: In one embodiment of the present invention, an electrostatic discharge withstand voltage evaluating device includes: an application device, including a first connecting section and a second connecting section, for supplying pulse electric charge, the first connecting section being connectable to one or whole terminal(s) of one of input terminals and output terminals of a source driver, and supplying electric charge to the source driver, the second connecting section being connectable to one or whole terminal(s) of the other one of the input terminals and the output terminals, and enabling said one or whole terminal(s) of the other one of the input terminals and the output terminals to be grounded; and a common connecting section being connectable to the plurality of output terminals of the source driver, and causing the plurality of output terminals to be electrically connected to each other, wherein the output terminals of the source driver are connected, via the common connecting section, to one of the firs

Abstract: A semiconductor device has a semiconductor substrate of a first conductivity; and a first electrode formation region and a second electrode formation region formed adjacent to an inner surface of the semiconductor substrate. The first electrode formation regions and the second electrode formation regions are isolated from each other via an element isolation region. An upper first-type impurity layer and a lower first-type impurity layer are formed in one of the first electrode formation region and the second electrode formation region, the lower first-type impurity layer has a different first-type impurity concentration from the upper first-type impurity layer and is formed under the upper first-type impurity layer. A second-type impurity layer and a first-type impurity layer are formed in the other electrode formation region and the first-type impurity layer is formed under a part of the second-type impurity layer having second-type impurities.

Abstract: A semiconductor device comprising an electrostatic protective element of the semiconductor device including a first conductivity type substrate and a second conductivity type high concentration diffusion layer formed on a surface of the substrate, and a semiconductor element including a source/drain and a gate electrode, wherein a first conductivity type diffusion layer having a higher concentration than the first conductivity type substrate is provided in an entire region under the second conductivity type high concentration diffusion layer.

Abstract: An internal power voltage generating circuit of a semiconductor device includes a voltage dividing circuit composed of a single field effect transistor and a plurality of resistances incorporated into a semiconductor chip. The voltage dividing circuit divides an externally supplied power voltage into two types of voltage by conducting or non-conducting the single field effect transistor. The divided voltages are supplied as an internal power voltage to a plurality of field effect transistors incorporated into the semiconductor chip.

Abstract: An internal power voltage generating circuit of a semiconductor device includes a voltage dividing circuit composed of a single field effect transistor and a plurality of resistances incorporated into a semiconductor chip. The voltage dividing circuit divides an externally supplied power voltage into two types of voltage by conducting or non-conducting the single field effect transistor. The divided voltages are supplied as an internal power voltage to a plurality of field effect transistors incorporated into the semiconductor chip.

Abstract: A semiconductor device comprising: a first wiring layer formed on a semiconductor substrate with an insulation film interposed therebetween, an interlayer insulation film and a second wiring layer formed on the first wiring layer in this order, wherein the interlayer insulation film is composed, from a first wiring layer side, of a first silicon oxide film having a compressive stress within the film, a silicon nitride film having a compressive stress within the film, a second silicon oxide film having a tensile stress within the film, and a third silicon oxide film having a compressive stress within the film.

Abstract: A semiconductor device comprising an electrostatic protective element of the semiconductor device including a first conductivity type substrate and a second conductivity type high concentration diffusion layer formed on a surface of the substrate, and a semiconductor element including a source/drain and a gate electrode, wherein a first conductivity type diffusion layer having a higher concentration than the first conductivity type substrate is provided in an entire region under the second conductivity type high concentration diffusion layer.

Abstract: A process of manufacturing a semiconductor device comprising: a step of forming an interlayer insulating film so as to cover a plurality of semiconductor elements formed on a semiconductor substrate, a step of forming openings in predetermined regions of the interlayer insulating film on the semiconductor elements in a manner of penetrating only halfway through the interlayer insulating film, a dual damascene step of forming contact hole by removing the interlayer insulating film remaining under the predetermined ones of the openings, thereby forming simultaneously openings for burying a wiring layer which include upper portions of the predetermined openings, a step of forming a conductive layer on the interlayer insulating film to fill at least the contact holes and the openings for burying the wiring layer; and a step of forming contact plugs and a buried wiring layer by removing the conductive layer on the interlayer insulating film.

Abstract: A semiconductor device comprising: a first wiring layer formed on a semiconductor substrate with an insulation film interposed therebetween, an interlayer insulation film and a second wiring layer formed on the first wiring layer in this order, wherein the interlayer insulation film is composed, from a first wiring layer side, of a first silicon oxide film having a compressive stress within the film, a silicon nitride film having a compressive stress within the film, a second silicon oxide film having a tensile stress within the film, and a third silicon oxide film having a compressive stress within the film.

Abstract: A process for producing a semiconductor device comprises the steps of: (a) forming a gate electrode on N channel and P channel transistors forming regions (N-Tr region and P-Tr region) on a semiconductor substrate; (b) forming a side wall spacer on a side wall of the gate electrode; (c) covering the P-Tr region with a resist, and forming a source/drain region on the N-Tr region by ion implantation using the resist, the gate electrode and the side wall spacer as a mask; (d) removing a part of the side wall spacer of the gate electrode in the N-Tr region; (e) forming an LDD region on the N-Tr region by ion implantation using the resist, the gate electrode and the resulting side wall spacer as a mask; (f) removing the resist; (g) covering the N-Tr region with a resist, and forming a source/drain region on the P-Tr region by ion implantation using the resist, the gate electrode and the side wall spacer as a mask; (h) removing a part of the side wall spacer of the gate electrode in the P-Tr region; and (i) forming

Abstract: A method for manufacturing a semiconductor device including steps of (i) laminating a first insulating film over a semiconductor substrate having a plurality of gate electrodes, on which side walls are at least formed, through capacitor formation regions, removing the first insulating film in the capacitor formation region so as to form a direct contact, and laminating a first conductive film over the semiconductor substrate including the residual first insulating film, (ii) removing the first conductive film with remaining at least in the capacitor formation region, (iii) sequentially laminating over the semiconductor substrate including the residual first conductive film (a) a second insulating film, a second conductive film and a third insulating film, or (b) a second insulating film and a second conductive film, and then laminating a resist layer over the whole surface, and (iv) patterning the resist layer and removing with the use of a resist pattern (a) the third insulating film, second conductive film,