Abstract: A system may include a first controller and a second controller communicatively coupled to the first controller via a bidirectional communication channel and configured to drive a load in accordance with a target current signal, sample a load voltage of the load at a sample rate substantially slower than a time duration of electrical transients of the load, calculate a resistance of the load based on a current signal and the load voltage and communicate information indicative of the resistance to the first controller at a time interval substantially slower than the time duration of electrical transients of the load, detect when one or more accuracy-reducing events associated with the system occur, wherein an accuracy-reducing event is one which negatively affects accuracy of calculation of the resistance, and modify the information provided to the first controller when one or more accuracy-reducing events occur.

Abstract: A system may include a plurality of processing cores including at least a first processing core and a second processing core, a shared memory communicatively coupled to and accessible by each of the plurality of processing cores, a global monitor communicatively coupled to each of the plurality of processing cores and configured to control exclusive accesses to memory by each of the plurality of processing cores, and a software architecture embodied in non-transitory computer-readable media and configured to, when read and executed by the multicore processor, partition a plurality of processing tasks between the first processing core and the second processing core.

Abstract: A processor and processing method for reusing arbitrary sections of program code provides improved upgrade capability for systems with non-alterable read only memory (ROM) and a more flexible instruction set in general. A specific program instruction is provided in the processor instruction set for directing program execution to a particular start address, where the start address is specified in conjunction with the specific program instruction. An end address is also specified in conjunction with the specific program instruction and the processor re-directs control upon completion of code execution between the start and end address to either another specified address, or to a stored program counter value corresponding to the next instruction in sequence after the specific program instruction. A loop count may also be supplied for repeatedly executing the code between the start and end address until the count has expired.