Patents by Inventor Narumasa Soejima

Narumasa Soejima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967564
    Abstract: A method for manufacturing a semiconductor device includes: forming an insulating film on a surface of a semiconductor layer of a semiconductor substrate; forming a contact hole in the insulating film; forming a conductor material on the insulating film to be in contact with the semiconductor layer through the contact hole; and patterning the conductor material using an alignment key included in the conductor material.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: April 23, 2024
    Assignee: DENSO CORPORATION
    Inventors: Aiko Kaji, Haruhito Ichikawa, Shuhei Mitani, Tomohiro Mimura, Yukihiro Wakasugi, Narumasa Soejima
  • Patent number: 11171231
    Abstract: A silicon carbide semiconductor device includes a semiconductor element with a MOS structure having: a substrate; a drift layer on the substrate; a base region on the drift layer; a source region on the base region; a trench gate structure having a gate insulation film and a gate electrode in a gate trench disposed from a surface of the source region to be deeper than the base region; an interlayer insulation film covering the gate electrode and the gate insulation film; a source electrode on the interlayer insulation film, the source region and the base region; and a drain electrode. The semiconductor element flows a current when a gate voltage is applied to the gate electrode and a channel region is provided in a portion of the base region in contact with the trench gate structure.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: November 9, 2021
    Assignee: DENSO CORPORATION
    Inventors: Shuhei Mitani, Masahiro Kumita, Narumasa Soejima
  • Patent number: 11107691
    Abstract: A method of manufacturing a semiconductor device is provided, and the method may include: preparing a semiconductor substrate constituted of a group III nitride semiconductor, a main surface of the semiconductor substrate being a c-plane; forming a grove on the main surface by dry dry-etching the main surface; and wet-etching an inner surface of the groove using an etchant to expose the c-plane of the semiconductor substrate in a wet-etched region, the etching having an etching rate to the c-plane of the semiconductor substrate that is lower than the etching rate to a plane other than the c-plane of the semiconductor substrate.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: August 31, 2021
    Assignee: DENSO CORPORATION
    Inventors: Toru Ikeda, Tomohiko Mori, Narumasa Soejima, Hideya Yamadera
  • Publication number: 20210151385
    Abstract: A method for manufacturing a semiconductor device includes: forming an insulating film on a surface of a semiconductor layer of a semiconductor substrate; forming a contact hole in the insulating film; forming a conductor material on the insulating film to be in contact with the semiconductor layer through the contact hole; and patterning the conductor material using an alignment key included in the conductor material.
    Type: Application
    Filed: January 27, 2021
    Publication date: May 20, 2021
    Inventors: Aiko KAJI, Haruhito ICHIKAWA, Shuhei MITANI, Tomohiro MIMURA, Yukihiro WAKASUGI, Narumasa SOEJIMA
  • Publication number: 20200365409
    Abstract: A method of manufacturing a semiconductor device is provided, and the method may include: preparing a semiconductor substrate constituted of a group III nitride semiconductor, a main surface of the semiconductor substrate being a c-plane; forming a grove on the main surface by dry dry-etching the main surface; and wet-etching an inner surface of the groove using an etchant to expose the c-plane of the semiconductor substrate in a wet-etched region, the etching having an etching rate to the c-plane of the semiconductor substrate that is lower than the etching rate to a plane other than the c-plane of the semiconductor substrate.
    Type: Application
    Filed: April 29, 2020
    Publication date: November 19, 2020
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Toru IKEDA, Tomohiko Mori, Narumasa Soejima, Hideya Yamadera
  • Publication number: 20200203526
    Abstract: A silicon carbide semiconductor device includes a semiconductor element with a MOS structure having: a substrate; a drift layer on the substrate; a base region on the drift layer; a source region on the base region; a trench gate structure having a gate insulation film and a gate electrode in a gate trench disposed from a surface of the source region to be deeper than the base region; an interlayer insulation film covering the gate electrode and the gate insulation film; a source electrode on the interlayer insulation film, the source region and the base region; and a drain electrode. The semiconductor element flows a current when a gate voltage is applied to the gate electrode and a channel region is provided in a portion of the base region in contact with the trench gate structure.
    Type: Application
    Filed: February 28, 2020
    Publication date: June 25, 2020
    Inventors: Shuhei MITANI, Masahiro KUMITA, Narumasa SOEJIMA
  • Patent number: 10593662
    Abstract: A protection device includes a semiconductor substrate including a protection element; an insulating layer covering a surface of the semiconductor substrate; a conductive layer disposed in the insulating layer, and extending in a plane that is parallel with the surface of the semiconductor substrate; a passive element formed with an elongated conductor, curved in a plane that is parallel with the conductive layer, and located over the conductive layer; and an input terminal, an output terminal, and a ground terminal exposed in a surface of the insulating layer. One end of the passive element is electrically connected to the input terminal, the other end of the passive element and a high-potential-side terminal of the protection element are electrically connected to the output terminal, and a low-potential-side terminal of the protection element and the conductive layer are electrically connected to the ground terminal.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: March 17, 2020
    Assignee: KABUSHIKI KAISHA TOKAI RIKA DENKI SEISAKUSHO
    Inventors: Narumasa Soejima, Takashi Suzuki, Kengo Shima, Yosuke Kanie, Kazuya Adachi
  • Patent number: 10522627
    Abstract: A semiconductor device may be provided with a semiconductor substrate, an upper electrode, a lower electrode and a gate electrode provided within a trench via a gate insulator film. The semiconductor substrate may include a p-type body layer being in contact with the upper electrode, an n-type drift layer intervening between the body layer and the lower electrode, a p-type floating region provided along a bottom surface of the trench, and a p-type connection region extending between the body layer and the floating region along a side surface of the trench. The trench may include a first section where the connection region is not provided and a second section where the connection region is provided. An inclination angle of the side surface of the trench in the second section may be greater than an inclination angle of the side surface of the trench in the first section.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: December 31, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidefumi Takaya, Yasushi Urakami, Narumasa Soejima
  • Patent number: 10388527
    Abstract: A method of manufacturing a semiconductor device is provided with: implanting charged particles including oxygen into a surface of a SiC wafer; and forming a Schottky electrode that makes Schottky contact with the SiC wafer on the surface after the implantation of the charged particles.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: August 20, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Norihiro Togawa, Narumasa Soejima, Shoji Mizuno
  • Patent number: 10290707
    Abstract: A semiconductor device includes: a drain region; a drift layer made of a first conductivity type semiconductor with lower impurity concentration than the drain region; a base region made of a second conductivity type semiconductor; a source region made of the first conductivity type semiconductor with higher concentration; a contact region made of the second conductivity type semiconductor with higher concentration; a trench structure having a first gate insulation film and a first gate electrode arranged at an opening side of the trench and to be deeper than the base region, and a bottom part insulation film; a source electrode electrically connected to the source and contact regions; and a drain electrode at a rear side of the drain region. The drain is arranged to be deeper than the base region. The first gate insulation film is made of higher dielectric insulation material than the bottom part insulation film.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: May 14, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tomohiro Mimura, Takashi Kanemura, Masahiro Sugimoto, Narumasa Soejima
  • Publication number: 20190067420
    Abstract: A semiconductor device may be provided with a semiconductor substrate, an upper electrode, a lower electrode and a gate electrode provided within a trench via a gate insulator film. The semiconductor substrate may include a p-type body layer being in contact with the upper electrode, an n-type drift layer intervening between the body layer and the lower electrode, a p-type floating region provided along a bottom surface of the trench, and a p-type connection region extending between the body layer and the floating region along a side surface of the trench. The trench may include a first section where the connection region is not provided and a second section where the connection region is provided. An inclination angle of the side surface of the trench in the second section may be greater than an inclination angle of the side surface of the trench in the first section.
    Type: Application
    Filed: July 5, 2018
    Publication date: February 28, 2019
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidefumi TAKAYA, Yasushi URAKAMI, Narumasa SOEJIMA
  • Patent number: 10177236
    Abstract: A method of manufacturing a semiconductor device includes: setting a plurality of main semiconductor wafers and a plurality of sub semiconductor wafers in a load lock chamber of an electrode forming equipment; repeating a wafer-transfer and electrode-formation process of transferring at least one of the main semiconductor wafers from the load lock chamber to the film formation chamber in a state where the load lock chamber and the film formation chamber are decompressed and then forming a surface electrode on a surface of the at least one main semiconductor wafer transferred in the film formation chamber; removing the main semiconductor wafers on which the surface electrodes have been formed and the sub semiconductor wafers from the electrode forming equipment without forming an electrode on the sub semiconductor wafers by the electrode forming equipment; and making the surface electrodes Schottky-contact the main semiconductor wafers.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: January 8, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Teruaki Kumazawa, Narumasa Soejima, Yuichi Takeuchi
  • Patent number: 10177138
    Abstract: A semiconductor device used in a protection circuit including a thyristor and an LCR circuit which includes a coil L, a capacitor C and a resistor R, the semiconductor device may include: a semiconductor layer in which the thyristor is provided; an insulating film provided on the semiconductor layer; and a pair of electrodes provided on the insulating film and connected to a protection target circuit, wherein at least one of the coil L, the capacitor C and the resistor R is provided in the insulating film, and the at least one of the coil L, the capacitor C and the resistor R is connected to an anode of the thyristor by a first metal wire filling a first hole provided in the insulating film.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: January 8, 2019
    Assignees: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, KABUSHIKI KAISHA TOKAI RIKA DENKI SEISAKUSHO
    Inventors: Takashi Suzuki, Narumasa Soejima, Yosuke Kanie, Kengo Shima
  • Publication number: 20180261592
    Abstract: A protection device includes: a semiconductor substrate in which a protection element; an insulating layer covering a surface of the semiconductor substrate; a conductive layer disposed in the insulating layer, and extending in a plane that is parallel with the surface of the semiconductor substrate; a passive element formed with an elongated conductor, curved in a plane that is parallel with the conductive layer, and located over the conductive layer; and an input terminal, an output terminal, and a ground terminal exposed in a surface of the insulating layer. One end of the passive element is electrically connected to the input terminal, the other end of the passive element and a high-potential-side terminal of the protective element are electrically connected to the output terminal, and a low-potential-side terminal of the protective element and the conductive layer are electrically connected to the ground terminal.
    Type: Application
    Filed: March 8, 2018
    Publication date: September 13, 2018
    Applicant: KABUSHIKI KAISHA TOKAI RIKA DENKI SEISAKUSHO
    Inventors: Narumasa SOEJIMA, Takashi SUZUKI, Kengo SHIMA, Yosuke KANIE, Kazuya ADACHI
  • Publication number: 20180233497
    Abstract: A semiconductor device used in a protection circuit including a thyristor and an LCR circuit which includes a coil L, a capacitor C and a resistor R, the semiconductor device may include: a semiconductor layer in which the thyristor is provided; an insulating film provided on the semiconductor layer; and a pair of electrodes provided on the insulating film and connected to a protection target circuit, wherein at least one of the coil L the capacitor C and the resistor R is provided in the insulating film, and the at least one of the coil L, the capacitor C and the resistor R is connected to an anode of the thyristor by a first metal wire filling a first hole provided in the insulating film.
    Type: Application
    Filed: January 29, 2018
    Publication date: August 16, 2018
    Applicants: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, KABUSHIKI KAISHA TOKAI RIKA DENKI SEISAKUSHO
    Inventors: Takashi SUZUKI, Narumasa SOEJIMA, Yosuke KANIE, Kengo SHIMA
  • Publication number: 20180145144
    Abstract: A method of manufacturing a semiconductor device includes: setting a plurality of main semiconductor wafers and a plurality of sub semiconductor wafers in a load lock chamber of an electrode forming equipment; repeating a wafer-transfer and electrode-formation process of transferring at least one of the main semiconductor wafers from the load lock chamber to the film formation chamber in a state where the load lock chamber and the film formation chamber are decompressed and then forming a surface electrode on a surface of the at least one main semiconductor wafer transferred in the film formation chamber; removing the main semiconductor wafers on which the surface electrodes have been formed and the sub semiconductor wafers from the electrode forming equipment without forming an electrode on the sub semiconductor wafers by the electrode forming equipment; and making the surface electrodes Schottky-contact the main semiconductor wafers.
    Type: Application
    Filed: October 16, 2017
    Publication date: May 24, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Teruaki KUMAZAWA, Narumasa SOEJIMA, Yuichi TAKEUCHI
  • Publication number: 20180144938
    Abstract: A method of manufacturing a semiconductor device is provided with: implanting charged particles including oxygen into a surface of a SiC wafer; and forming a Schottky electrode that makes Schottky contact with the SiC wafer on the surface after the implantation of the charged particles.
    Type: Application
    Filed: October 6, 2017
    Publication date: May 24, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Norihiro TOGAWA, Narumasa SOEJIMA, Shoji MIZUNO
  • Patent number: 9954096
    Abstract: A switching device includes a semiconductor substrate; a trench; a conductor layer extending in a longitudinal direction of the trench so as to be in contact with a bottom surface of the trench; a bottom insulating layer covering an upper surface of the conductor layer; a gate insulating layer covering a side surface of the trench; and a gate electrode disposed in the trench. The semiconductor substrate includes a first semiconductor region of a first conductivity type, a body region of a second conductivity type, a second semiconductor region of the first conductivity type, a bottom semiconductor region of the second conductivity type extending in the longitudinal direction so as to be in contact with the conductor layer, and a connection semiconductor region of the second conductivity type connected to the body region and to the bottom semiconductor region.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: April 24, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hirokazu Fujiwara, Yuichi Takeuchi, Narumasa Soejima
  • Publication number: 20180097061
    Abstract: A semiconductor device includes: a drain region; a drift layer made of a first conductivity type semiconductor with lower impurity concentration than the drain region; a base region made of a second conductivity type semiconductor; a source region made of the first conductivity type semiconductor with higher concentration; a contact region made of the second conductivity type semiconductor with higher concentration; a trench structure having a first gate insulation film and a first gate electrode arranged at an opening side of the trench and to be deeper than the base region, and a bottom part insulation film; a source electrode electrically connected to the source and contact regions; and a drain electrode at a rear side of the drain region. The drain is arranged to be deeper than the base region. The first gate insulation film is made of higher dielectric insulation material than the bottom part insulation film.
    Type: Application
    Filed: March 10, 2016
    Publication date: April 5, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tomohiro MIMURA, Takashi KANEMURA, Masahiro SUGIMOTO, Narumasa SOEJIMA
  • Publication number: 20180090612
    Abstract: A switching device includes a semiconductor substrate; a trench; a conductor layer extending in a longitudinal direction of the trench so as to be in contact with a bottom surface of the trench; a bottom insulating layer covering an upper surface of the conductor layer; a gate insulating layer covering a side surface of the trench; and a gate electrode disposed in the trench. The semiconductor substrate includes a first semiconductor region of a first conductivity type, a body region of a second conductivity type, a second semiconductor region of the first conductivity type, a bottom semiconductor region of the second conductivity type extending in the longitudinal direction so as to be in contact with the conductor layer, and a connection semiconductor region of the second conductivity type connected to the body region and to the bottom semiconductor region.
    Type: Application
    Filed: July 31, 2017
    Publication date: March 29, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hirokazu FUJIWARA, Yuichi TAKEUCHI, Narumasa SOEJIMA