Patents by Inventor Natalie B. Feilchenfeld
Natalie B. Feilchenfeld has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10535551Abstract: Lateral PiN diodes and Schottky diodes with low parasitic capacitance and variable breakdown voltage structures and methods of manufacture are disclosed. The structure includes a diode with breakdown voltage determined by a dimension between p-and n-terminals formed in an i-region above a substrate.Type: GrantFiled: March 13, 2018Date of Patent: January 14, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Natalie B. Feilchenfeld, Vibhor Jain, Qizhi Liu
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Patent number: 10446644Abstract: Methods for forming a device structure and device structures using a silicon-on-insulator substrate that includes a high-resistance handle wafer. A doped region is formed in the high-resistance handle wafer. A first trench is formed that extends through a device layer and a buried insulator layer of the silicon-on-insulator substrate to the high-resistance handle wafer. The doped region includes lateral extension of the doped region extending laterally of the first trench. A semiconductor layer is epitaxially grown within the first trench, and a device structure is formed using at least a portion of the semiconductor layer. A second trench is formed that extends through the device layer and the buried insulator layer to the lateral extension of the doped region, and a conductive plug is formed in the second trench. The doped region and the plug comprise a body contact.Type: GrantFiled: June 22, 2015Date of Patent: October 15, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Renata Camillo-Castillo, Hanyi Ding, Natalie B. Feilchenfeld, Vibhor Jain, Anthony K. Stamper
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Patent number: 10050115Abstract: Approaches for LDMOS devices are provided. A method of forming a semiconductor structure includes forming a gate dielectric including a first portion having a first uniform thickness, a second portion having a second uniform thickness different than the first uniform thickness, and a transition portion having tapered surface extending from the first portion to the second portion. The gate dielectric is formed on a planar upper surface of a substrate. The tapered surface is at an acute angle relative to the upper surface of the substrate.Type: GrantFiled: December 30, 2014Date of Patent: August 14, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Brennan J. Brown, Natalie B. Feilchenfeld, Max G. Levy, Santosh Sharma, Yun Shi, Michael J. Zierak
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Publication number: 20180204761Abstract: Lateral PiN diodes and Schottky diodes with low parasitic capacitance and variable breakdown voltage structures and methods of manufacture are disclosed. The structure includes a diode with breakdown voltage determined by a dimension between p- and n-terminals formed in an i-region above a substrate.Type: ApplicationFiled: March 13, 2018Publication date: July 19, 2018Inventors: Natalie B. FEILCHENFELD, Vibhor JAIN, Qizhi LIU
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Patent number: 9947573Abstract: Lateral PiN diodes and Schottky diodes with low parasitic capacitance and variable breakdown voltage structures and methods of manufacture are disclosed. The structure includes a diode with breakdown voltage determined by a dimension between p- and n-terminals formed in an i-region above a substrate.Type: GrantFiled: September 3, 2014Date of Patent: April 17, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Natalie B. Feilchenfeld, Vibhor Jain, Qizhi Liu
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Patent number: 9893157Abstract: Structures that include contact trenches and isolation trenches, as well as methods for forming structures including contact trenches and isolation trenches. A contact trench is formed that extends through a device layer of a silicon-on-insulator (SOI) substrate to a buried oxide layer of the SOI substrate. An isolation trench is formed that extends through the device layer to the buried oxide layer. An electrical insulator is deposited that fills the contact trench and the first isolation trench. The electrical insulator is removed from the contact trench. After the electrical insulator is removed from the contact trench, an electrical conductor is formed in the contact trench. The electrical contact may be coupled with a doped region in a handle wafer of the SOI substrate.Type: GrantFiled: January 9, 2017Date of Patent: February 13, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Natalie B. Feilchenfeld, Michael J. Zierak, Max G. Levy, BethAnn Lawrence
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Patent number: 9799652Abstract: Disclosed are methods that employ a mask with openings arranged in a pattern of elongated trenches and holes of varying widths to achieve a linearly graded conductivity level. These methods can be used to form a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a drain drift region having an appropriate type conductivity at a level that increases essentially linearly from the body region to the drain region. Furthermore, these methods also provide for improve manufacturability in that multiple instances of this same pattern can be used during a single dopant implant process to implant a first dopant with a first type (e.g., N-type) conductivity into the drain drift regions of both first and second type LDMOSFETs (e.g., N and P-type LDMOSFETs, respectively). In this case, the drain drift region of a second type LDMOSFET can subsequently be uniformly counter-doped. Also disclosed are the resulting semiconductor structures.Type: GrantFiled: June 28, 2017Date of Patent: October 24, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Natalie B. Feilchenfeld, Michael J. Zierak, Theodore J. Letavic, Yun Shi, Santosh Sharma
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Patent number: 9786606Abstract: A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two. The structure includes first and second openings each having sidewalls, each of the first opening and the second opening formed substantially simultaneously and extending from a top surface of the semiconductor layer through the semiconductor layer and through the insulation layer to the conductive region; an insulating material adapted to provide electrical insulation to at least a portion of the side walls of the first opening; a semiconductor material at least partially filling the first opening, the semiconductor material defining an ohmic contact trench providing electrical contact with the semiconductor region; and an insulating material disposed in the second opening and defining a device isolation trench.Type: GrantFiled: March 10, 2016Date of Patent: October 10, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Natalie B. Feilchenfeld, BethAnn Lawrence, Yun Shi
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Patent number: 9768028Abstract: Disclosed are methods that employ a mask with openings arranged in a pattern of elongated trenches and holes of varying widths to achieve a linearly graded conductivity level. These methods can be used to form a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a drain drift region having an appropriate type conductivity at a level that increases essentially linearly from the body region to the drain region. Furthermore, these methods also provide for improve manufacturability in that multiple instances of this same pattern can be used during a single dopant implant process to implant a first dopant with a first type (e.g., N-type) conductivity into the drain drift regions of both first and second type LDMOSFETs (e.g., N and P-type LDMOSFETs, respectively). In this case, the drain drift region of a second type LDMOSFET can subsequently be uniformly counter-doped. Also disclosed are the resulting semiconductor structures.Type: GrantFiled: August 10, 2016Date of Patent: September 19, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Natalie B. Feilchenfeld, Michael J. Zierak, Theodore J. Letavic, Yun Shi, Santosh Sharma
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Patent number: 9595579Abstract: Various embodiments include structures for field effect transistors (FETs). In various embodiments, a structure for a FET includes: a deep n-type well; a shallow n-type well within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well, and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.Type: GrantFiled: May 14, 2015Date of Patent: March 14, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Natalie B. Feilchenfeld, Max G. Levy, Richard A. Phelps, Santosh Sharma, Yun Shi, Michael J. Zierak
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Publication number: 20160372582Abstract: Methods for forming a device structure and device structures using a silicon-on-insulator substrate that includes a high-resistance handle wafer. A doped region is formed in the high-resistance handle wafer. A first trench is formed that extends through a device layer and a buried insulator layer of the silicon-on-insulator substrate to the high-resistance handle wafer. The doped region includes lateral extension of the doped region extending laterally of the first trench. A semiconductor layer is epitaxially grown within the first trench, and a device structure is formed using at least a portion of the semiconductor layer. A second trench is formed that extends through the device layer and the buried insulator layer to the lateral extension of the doped region, and a conductive plug is formed in the second trench. The doped region and the plug comprise a body contact.Type: ApplicationFiled: June 22, 2015Publication date: December 22, 2016Inventors: Renata Camillo-Castillo, Hanyi Ding, Natalie B. Feilchenfeld, Vibhor Jain, Anthony K. Stamper
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Publication number: 20160190269Abstract: Approaches for LDMOS devices are provided. A method of forming a semiconductor structure includes forming a gate dielectric including a first portion having a first uniform thickness, a second portion having a second uniform thickness different than the first uniform thickness, and a transition portion having tapered surface extending from the first portion to the second portion. The gate dielectric is formed on a planar upper surface of a substrate. The tapered surface is at an acute angle relative to the upper surface of the substrate.Type: ApplicationFiled: December 30, 2014Publication date: June 30, 2016Inventors: Brennan J. Brown, Natalie B. Feilchenfeld, Max G. Levy, Santosh Sharma, Yun Shi, Michael J. Zierak
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Publication number: 20160190067Abstract: A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two. The structure includes first and second openings each having sidewalls, each of the first opening and the second opening formed substantially simultaneously and extending from a top surface of the semiconductor layer through the semiconductor layer and through the insulation layer to the conductive region; an insulating material adapted to provide electrical insulation to at least a portion of the side walls of the first opening; a semiconductor material at least partially filling the first opening, the semiconductor material defining an ohmic contact trench providing electrical contact with the semiconductor region; and an insulating material disposed in the second opening and defining a device isolation trench.Type: ApplicationFiled: March 10, 2016Publication date: June 30, 2016Inventors: Natalie B. Feilchenfeld, BethAnn Lawrence, Yun Shi
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Patent number: 9324632Abstract: A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two. The method includes substantially simultaneously forming a first opening and a second opening extending from the semiconductor layer to the conductive region; introducing an insulating material to the side walls of the first opening; at least partially filling the first opening with a semiconductor material to provide an ohmic contact trench; and at least partially filling the second opening with an insulating material to form a device isolation trench. Insulating regions, for example, shallow trench isolation (STI) regions, may be formed about the device isolation trench and the ohmic contact trench. Semiconductor structures are also provided.Type: GrantFiled: May 28, 2014Date of Patent: April 26, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Natalie B. Feilchenfeld, BethAnn Lawrence, Yun Shi
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Publication number: 20160064475Abstract: Lateral PiN diodes and Schottky diodes with low parasitic capacitance and variable breakdown voltage structures and methods of manufacture are disclosed. The structure includes a diode with breakdown voltage determined by a dimension between p- and n-terminals formed in an i-region above a substrate.Type: ApplicationFiled: September 3, 2014Publication date: March 3, 2016Inventors: Natalie B. FEILCHENFELD, Vibhor JAIN, Qizhi LIU
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Publication number: 20160043202Abstract: A collector region is formed between insulating shallow trench isolation regions within a substrate. A base material is epitaxially grown on the collector region and the shallow trench isolation regions. The base material forms a base region on the collector region and extrinsic base regions on the shallow trench isolation regions. Further, a sacrificial emitter structure is patterned on the base region and sidewall spacers are formed on the sacrificial emitter structure. Planar raised base structures are epitaxially grown on the base region and the extrinsic base regions, and the upper layer of the raised base structures is oxidized. The sacrificial emitter structure is removed to leave an open space between the sidewall spacers and an emitter is formed within the open space between the sidewall spacers. The upper layer of the raised base structures comprises a planar insulator electrically insulating the emitter from the raised base structures.Type: ApplicationFiled: October 26, 2015Publication date: February 11, 2016Inventors: Natalie B. Feilchenfeld, Qizhi Liu
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Publication number: 20150348870Abstract: A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two. The method includes substantially simultaneously forming a first opening and a second opening extending from the semiconductor layer to the conductive region; introducing an insulating material to the side walls of the first opening; at least partially filling the first opening with a semiconductor material to provide an ohmic contact trench; and at least partially filling the second opening with an insulating material to form a device isolation trench. Insulating regions, for example, shallow trench isolation (STI) regions, may be formed about the device isolation trench and the ohmic contact trench. Semiconductor structures are also provided.Type: ApplicationFiled: May 28, 2014Publication date: December 3, 2015Applicant: International Business Machines CorporationInventors: Natalie B. Feilchenfeld, BethAnn Lawrence, Yun Shi
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Patent number: 9202869Abstract: A collector region is formed between insulating shallow trench isolation regions within a substrate. A base material is epitaxially grown on the collector region and the shallow trench isolation regions. The base material forms a base region on the collector region and extrinsic base regions on the shallow trench isolation regions. Further, a sacrificial emitter structure is patterned on the base region and sidewall spacers are formed on the sacrificial emitter structure. Planar raised base structures are epitaxially grown on the base region and the extrinsic base regions, and the upper layer of the raised base structures is oxidized. The sacrificial emitter structure is removed to leave an open space between the sidewall spacers and an emitter is formed within the open space between the sidewall spacers. The upper layer of the raised base structures comprises a planar insulator electrically insulating the emitter from the raised base structures.Type: GrantFiled: May 9, 2013Date of Patent: December 1, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Natalie B. Feilchenfeld, Qizhi Liu
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Publication number: 20150255539Abstract: Various embodiments include field effect transistor (FET) structures and methods of forming such structures. In various embodiments, an FET structure includes: a deep n-type well; a shallow n-type well within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well, and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.Type: ApplicationFiled: May 14, 2015Publication date: September 10, 2015Inventors: Natalie B. Feilchenfeld, Max G. Levy, Richard A. Phelps, Santosh Sharma, Yun Shi, Michael J. Zierak
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Patent number: 9059276Abstract: High-voltage LDMOS devices with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming an insulator layer of varying depth over a drift region and a body of a substrate. The method further includes forming a control gate and a split gate region by patterning a layer of material on the insulator layer. The split gate region is formed on a first portion of the insulator layer and the control gate is formed on a second portion of the insulator layer, which is thinner than the first portion.Type: GrantFiled: June 7, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Natalie B. Feilchenfeld, Theodore J. Letavic, Richard A. Phelps, Santosh Sharma, Yun Shi, Michael J. Zierak