Patents by Inventor Natarajan Viswanathan

Natarajan Viswanathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10402522
    Abstract: Aspects of the present disclosure address improved systems and methods for region-aware clustering in integrated circuit (IC) designs. Consistent with some embodiments, the method may include identifying a clustering region for each clock driver included in an IC design based on locations of sinks and blockages, and timing constraints. The CTS tool finds representative locations for each clock driver within their respective clustering regions. Given the representative location for each clock driver, the CTS tool applies point-based clustering to the clock drivers of the IC design to obtain one or more clusters.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: September 3, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Natarajan Viswanathan, Charles Jay Alpert, Thomas Andrew Newton, William Robert Reece
  • Patent number: 10318693
    Abstract: Aspects of the present disclosure address improved systems and methods for designing an integrated circuit design clock tree structure with scaled-load balanced clusters. Consistent with some embodiments, the system may include a clock tree synthesis (CTS) tool configured to recursively group pins to form a set of clusters that are balanced according to a scaled load. During the recursive grouping, the CTS tool scales actual loads of clusters in accordance with a scaling factor that is based on the radius of the cluster. In this way, the scaling factor penalizes large cluster spans during recursive clustering, thereby producing a clock tree structure that meets design rule constraints.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: June 11, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Natarajan Viswanathan, Zhuo Li, Charles Jay Alpert, William Robert Reece, Thomas Andrew Newton
  • Patent number: 10289797
    Abstract: Aspects of the present disclosure address improved systems and methods for local cluster refinement during clock tree synthesis for integrated circuit designs. In accordance with some embodiments, the methods for local cluster refinement may include pin move refinement and local reclustering. With pin move refinement, pins are moved from clusters that fail to satisfy design rule constraints to nearby clusters that satisfy design rule constraints. With local reclustering, groups of neighboring clusters that fail or nearly fail to satisfy design rule constraints are dissolved and corresponding pins are regrouped to form new clusters that satisfy design rule constraints.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Natarajan Viswanathan, Charles Jay Alpert, Wen-Hao Liu, Thomas Andrew Newton
  • Publication number: 20190026418
    Abstract: The disclosed herein relates to method for persistence during placement optimization of an integrated circuit design. The method comprises performing cluster operation by grouping of a plurality of cells into a plurality of mobs. The method further comprises performing a spreading operation by moving the plurality of mobs and the plurality of cells simultaneously to optimize empty space of the integrated circuit design.
    Type: Application
    Filed: September 25, 2018
    Publication date: January 24, 2019
    Inventors: Myung-Chul Kim, Shyam Ramji, Paul G. Villarrubia, Natarajan Viswanathan
  • Patent number: 10140409
    Abstract: The disclosed herein relates to method for persistence during placement optimization of an integrated circuit design. The method comprises performing cluster operation by grouping of a plurality of cells into a plurality of mobs. The method further comprises performing a spreading operation by moving the plurality of mobs and the plurality of cells simultaneously to optimize empty space of the integrated circuit design.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: November 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Myung-Chul Kim, Shyam Ramji, Paul G. Villarrubia, Natarajan Viswanathan
  • Patent number: 9870097
    Abstract: A differential sensing scheme provides a means for detecting one or more touch events on a touch sensitive device in the presence of incident noise. Instead of sensing one touch sensitive channel, such as a row, column, or single touch sensor, multiple touch sensitive channels are sampled at a time. By sampling two nearby channels simultaneously and doing the measurement differentially, noise common to both channels is cancelled. The differential sensing scheme is implemented using simple switch-capacitor AFE circuitry. The originally sensed data on each individual channel is recovered free of common-mode noise. The recovered sensed data is used to determine the presence of one or more touch events and if present the location of each touch event on the touch sensitive device.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: January 16, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Ashutosh Ravindra Joharapurkar, Jean CauXuan Le, Natarajan Viswanathan, Patrick Yin Chan
  • Publication number: 20170220722
    Abstract: The disclosed herein relates to method for persistence during placement optimization of an integrated circuit design. The method comprises performing cluster operation by grouping of a plurality of cells into a plurality of mobs. The method further comprises performing a spreading operation by moving the plurality of mobs and the plurality of cells simultaneously to optimize empty space of the integrated circuit design.
    Type: Application
    Filed: August 11, 2016
    Publication date: August 3, 2017
    Inventors: MYUNG-CHUL KIM, SHYAM RAMJI, PAUL G. VILLARRUBIA, NATARAJAN VISWANATHAN
  • Patent number: 9524363
    Abstract: An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: December 20, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Charles J. Alpert, Gi-Joon Nam, Chin Ngai Sze, Paul G. Villarrubia, Natarajan Viswanathan
  • Patent number: 9495501
    Abstract: The disclosed herein relates to method for persistence during placement optimization of an integrated circuit design. The method comprises performing cluster operation by grouping of a plurality of cells into a plurality of mobs. The method further comprises performing a spreading operation by moving the plurality of mobs and the plurality of cells simultaneously to optimize empty space of the integrated circuit design.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: November 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Myung-Chul Kim, Shyam Ramji, Paul G. Villarrubia, Natarajan Viswanathan
  • Publication number: 20160313863
    Abstract: A differential sensing scheme provides a means for detecting one or more touch events on a touch sensitive device in the presence of incident noise. Instead of sensing one touch sensitive channel, such as a row, column, or single touch sensor, multiple touch sensitive channels are sampled at a time. By sampling two nearby channels simultaneously and doing the measurement differentially, noise common to both channels is cancelled. The differential sensing scheme is implemented using simple switch-capacitor AFE circuitry. The originally sensed data on each individual channel is recovered free of common-mode noise. The recovered sensed data is used to determine the presence of one or more touch events and if present the location of each touch event on the touch sensitive device.
    Type: Application
    Filed: June 30, 2016
    Publication date: October 27, 2016
    Inventors: Ashutosh Ravindra Joharapurkar, Jean CauXuan Le, Natarajan Viswanathan, Patrick Yin Chan
  • Publication number: 20160291797
    Abstract: Random sampling techniques include techniques for reducing or eliminating errors in the output of capacitive sensor arrays such as touch panels. The channels of the touch panel are periodically sampled to determine the presence of one or more touch events. Each channel is individually sampled in a round robin fashion, referred to as a sampling cycle. During each sampling cycle, all channels are sampled once. Multiple sampling cycles are performed such that each channel is sampled multiple times. Random sampling techniques are used to sample each of the channels. One random sampling technique randomizes a starting channel in each sampling cycle. Another random sampling technique randomizes the selection of all channels in each sampling cycle. Yet another random sampling technique randomizes the sampling cycle delay period between each sampling cycle. Still another random sampling technique randomizes the channel delay period between sampling each channel.
    Type: Application
    Filed: June 7, 2016
    Publication date: October 6, 2016
    Inventors: Ashutosh Ravindra Joharapurkar, Patrick Yin Chan, David Allen, Natarajan Viswanathan
  • Patent number: 9442610
    Abstract: A differential sensing scheme provides a means for detecting one or more touch events on a touch sensitive device in the presence of incident noise. Instead of sensing one touch sensitive channel, such as a row, column, or single touch sensor, multiple touch sensitive channels are sampled at a time. By sampling two nearby channels simultaneously and doing the measurement differentially, noise common to both channels is cancelled. The differential sensing scheme is implemented using simple switch-capacitor AFE circuitry. The originally sensed data on each individual channel is recovered free of common-mode noise. The recovered sensed data is used to determine the presence of one or more touch events and if present the location of each touch event on the touch sensitive device.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: September 13, 2016
    Assignee: QUALCOMM Technologies, Inc.
    Inventors: Ashutosh R. Joharapurkar, Jean C. Le, Natarajan Viswanathan, Patrick Chan
  • Publication number: 20160209947
    Abstract: A differential sensing scheme provides a means for detecting one or more touch events on a touch sensitive device in the presence of incident noise. Instead of sensing one touch sensitive channel, such as a row, column, or single touch sensor, multiple touch sensitive channels are sampled at a time. By sampling two nearby channels simultaneously and doing the measurement differentially, noise common to both channels is cancelled. The differential sensing scheme is implemented using simple switch-capacitor AFE circuitry. The originally sensed data on each individual channel is recovered free of common-mode noise. The recovered sensed data is used to determine the presence of one or more touch events and if present the location of each touch event on the touch sensitive device.
    Type: Application
    Filed: July 3, 2013
    Publication date: July 21, 2016
    Inventors: Ashutosh R. Joharapurkar, Jean C. Le, Natarajan Viswanathan, Patrick Chan
  • Patent number: 9391607
    Abstract: Random sampling techniques include techniques for reducing or eliminating errors in the output of capacitive sensor arrays such as touch panels. The channels of the touch panel are periodically sampled to determine the presence of one or more touch events. Each channel is individually sampled in a round robin fashion, referred to as a sampling cycle. During each sampling cycle, all channels are sampled once. Multiple sampling cycles are performed such that each channel is sampled multiple times. Random sampling techniques are used to sample each of the channels. One random sampling technique randomizes a starting channel in each sampling cycle. Another random sampling technique randomizes the selection of all channels in each sampling cycle. Yet another random sampling technique randomizes the sampling cycle delay period between each sampling cycle. Still another random sampling technique randomizes the channel delay period between sampling each channel.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: July 12, 2016
    Assignee: QUALCOMM Technologies, Inc.
    Inventors: Ashutosh Ravindra Joharapurkar, Patrick Chan, David L. Allen, Natarajan Viswanathan
  • Patent number: 9251306
    Abstract: An automated method for aligning a critical datapath in an integrated circuit design inserts an artificial alignment net in the netlist which interconnects all cells in the bit stack of the datapath. The cells are placed using a wirelength optimization which assigns weights to wire sections based on the alignment direction. The rate of change of the alignment weighting value can vary during different stages of global placement. The invention is particularly suited for a force-directed placer which uses a linear system solver to obtain a globally optimum solution for placement of the cells having some overlap among the cells, and thereafter spreads the cells to reduce the overlap. Pseudo nets are also inserted which interconnect a cell and an expected location of the cell after spreading for that iteration.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 2, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Myung-Chul Kim, Natarajan Viswanathan, Samuel I. Ward
  • Patent number: 9098669
    Abstract: Boundary timing in the design of an integrated circuit is facilitated by designating a subset of boundary latches in the circuit, and applying placement constraints to the boundary latches. Global placement is performed while maintaining the boundary latch placement constraints, and a timing driven placement is performed after implementing timing assertions. Boundary latches are designated using a depth-first search to identify the first latches along interconnection paths with the PI/PO, and filtering out ineligible latches according to designer rules. A latch can be filtered out if it is in a large cluster of latches driven by a primary input or driving a primary output, if it drives too many POs, or is a feed-through latch. Constraints include movebounds, preplacement, or attractive forces between boundary latches and other boundary fixed objects, i.e., a fixed gate or a PI/PO.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: August 4, 2015
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Alpert, Mark D. Aubel, Gregory F. Ford, Zhuo Li, Chin Ngai Sze, Paul G. Villarrubia, Natarajan Viswanathan
  • Publication number: 20150199465
    Abstract: Boundary timing in the design of an integrated circuit is facilitated by designating a subset of boundary latches in the circuit, and applying placement constraints to the boundary latches. Global placement is performed while maintaining the boundary latch placement constraints, and a timing driven placement is performed after implementing timing assertions. Boundary latches are designated using a depth-first search to identify the first latches along interconnection paths with the PI/PO, and filtering out ineligible latches according to designer rules. A latch can be filtered out if it is in a large cluster of latches driven by a primary input or driving a primary output, if it drives too many POs, or is a feed-through latch. Constraints include movebounds, preplacement, or attractive forces between boundary latches and other boundary fixed objects, i.e., a fixed gate or a PI/PO.
    Type: Application
    Filed: January 10, 2014
    Publication date: July 16, 2015
    Applicant: International Business Machines Corporation
    Inventors: Charles J. Alpert, Mark D. Aubel, Gregory F. Ford, Zhuo Li, Chin Ngai Sze, Paul G. Villarrubia, Natarajan Viswanathan
  • Patent number: 8954912
    Abstract: A latch placement tool determines a shape for a cluster of latches from a preliminary layout (or based on a netlist), including an aspect ratio of the shape, and generates a template for placement of the latches in conformity with the shape. Latches are placed around a local clock buffer (LCB) based on latch size, from largest latch first to smallest latch last, and based on their ideal locations given the target aspect ratio. The ideal locations may be further based on the clock driver pin configuration of the LCB. The final template preferably has an aspect ratio that is approximately equal to the aspect ratio of the shape of the cluster, but the latch placement may be constrained by clock routing topology. Latch placement within a cluster can be further optimized by swapping one of the latches with another to minimize total wirelength of the design.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Shyam Ramji, Chin Ngai Sze, Paul G. Villarrubia, Natarajan Viswanathan
  • Patent number: 8830207
    Abstract: A touchscreen system for increasing the dynamic range of the system comprising a touchscreen coupled to an offset cancellation element and a capacitance measuring element. The offset cancellation element is configured to be dynamically changed in capacitance such that it offsets parasitic and sensor capacitances of the touchscreen sensors thereby leaving only touch event capacitance to be measured by the measuring element. The offset cancellation element is able to adjust to the initial unwanted capacitances of each sensor as well as dynamically adjust to changes in the unwanted capacitance due to the environment. In some embodiments, the offset cancellation element is a capacitance digital-to-analog converter that is controlled by a controller for offsetting the unwanted capacitance. As a result, the touchscreen system is able to utilize a small integrating capacitor thereby lowering cost and improving the dynamic range of the system.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: September 9, 2014
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Ashutosh R. Joharapurkar, Patrick Chan, David L. Allen, Natarajan Viswanathan
  • Patent number: 8793636
    Abstract: Mechanisms are provided for performing placement of cells in a design of a semiconductor device. An initial design of the semiconductor device is generated, the initial design comprising a first placement of cells. A preferred direction of placement associated with the cells is determined. The preferred direction is a direction along which spreading of the cells is preferred. A second design of the semiconductor device is generated by modifying the first placement of the cells to generate a second placement of cells, different from the first placement cells, based on the preferred direction of placement associated with the cells.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: July 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Alpert, Myung-Chul Kim, Zhuo Li, Natarajan Viswanathan, Samuel I. Ward