Patents by Inventor Nathan L. Kraft

Nathan L. Kraft has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8889511
    Abstract: In one general aspect, a method can include forming a shield dielectric layer in a trench in a semiconductor substrate, forming a shield electrode on at least a portion of the shield dielectric layer, and etching the shield dielectric layer so that a portion of the shield dielectric layer is recessed in the trench. The method can include forming a gate dielectric layer on the recessed portion of the shield dielectric layer in the trench, forming a first conductive gate electrode on a first side of the shield electrode and insulated from a first sidewall of the trench by the gate dielectric layer, and forming a second conductive gate electrode on a second side of the shield electrode and insulated from a second sidewall of the trench by the gate dielectric layer.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: November 18, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Nathan L. Kraft
  • Patent number: 8884365
    Abstract: A field effect transistor (FET) includes a body region of a first conductivity type disposed within a semiconductor region of a second conductivity type and a gate trench extending through the body region and terminating within the semiconductor region. The FET also includes a flared shield dielectric layer disposed in a lower portion of the gate trench, the flared shield dielectric layer including a flared portion that extends under the body region. The FET further includes a conductive shield electrode disposed in the trench and disposed, at least partially, within the flared shield dielectric.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: November 11, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
  • Publication number: 20130248991
    Abstract: A field effect transistor (FET) includes a body region of a first conductivity type disposed within a semiconductor region of a second conductivity type and a gate trench extending through the body region and terminating within the semiconductor region. The FET also includes a flared shield dielectric layer disposed in a lower portion of the gate trench, the flared shield dielectric layer including a flared portion that extends under the body region. The FET further includes a conductive shield electrode disposed in the trench and disposed, at least partially, within the flared shield dielectric.
    Type: Application
    Filed: May 10, 2013
    Publication date: September 26, 2013
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Hamza YILMAZ, Daniel CALAFUT, Christopher Boguslaw KOCON, Steven P. SAPP, Dean E. PROBST, Nathan L. KRAFT, Thomas E. GREBS, Rodney S. RIDLEY, Gary M. DOLNY, Bruce D. MARCHANT, Joseph A. YEDINAK
  • Patent number: 8441069
    Abstract: A field effect transistor includes a gate trench extending into a semiconductor region. The gate trench has a recessed gate electrode disposed therein. A source region in the semiconductor region flanks each side of the gate trench. A conductive material fills an upper portion of the gate trench so as to make electrical contact with the source regions along upper sidewalls of the gate trench. The conductive material is insulated from the recessed gate electrode.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: May 14, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
  • Publication number: 20120220091
    Abstract: A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film by a sub-atmospheric chemical vapor deposition process that fills the trench and covers a top surface of the substrate. The method also includes etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench.
    Type: Application
    Filed: March 12, 2012
    Publication date: August 30, 2012
    Inventors: Ashok Challa, Alan Elbanhawy, Thomas E. Grebs, Nathan L. Kraft, Dean E. Probst, Rodney S. Ridley, Steven P. Sapp, Qi Wang, Chongman Yun, J.G. Lee, Peter H. Wilson, Joseph A. Yedinak, J.Y. Jung, H.C. Jang, Babak S. Sani, Richard Stokes, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher L. Rexer, Christopher B. Kocon, Debra S. Woolsey
  • Publication number: 20120104490
    Abstract: A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.
    Type: Application
    Filed: October 21, 2011
    Publication date: May 3, 2012
    Inventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
  • Patent number: 8129245
    Abstract: Methods of manufacturing power semiconductor devices include forming an epitaxial and dielectric layer, patterning and etching the dielectric layer, forming a first oxide layer, forming a first conductive layer on top of the first oxide layer, etching the first conductive layer away inside an active trench, forming a second oxide layer and second conductive layer. The second conductive layer does not extend completely over the first conductive layer in a first region outside of the active trench. The methods further include forming a third oxide layer over the second conductive layer, etching a first opening through the third oxide layer exposing the second conductive layer outside the active trench, etching a second opening through the second oxide layer outside the active trench in the first region exposing the first conductive layer but not the second conductive layer, and filling the first and second openings with conductive material.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: March 6, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Nathan L. Kraft, Christopher B. Kocon, Richard Stokes
  • Publication number: 20110312138
    Abstract: Methods of manufacturing power semiconductor devices include forming trenches in a substrate, depositing a shield oxide layer that conforms to the trenches, depositing a gate polysilicon layer into the trenches, etching the gate polysilicon layer so that the gate polysilicon layer is recessed in the trench, etching the shield oxide layer so that the shield oxide layer is recessed in the trench and lower than the gate polysilicon layer, depositing a layer of gate oxide across the top of the substrate, sidewalls of the trenches and troughs inside the trenches leaving a recess, depositing shield polysilicon in the recess, etching the shield polysilicon layer so that the shield polysilicon layer is recessed in the trench and higher than the gate polysilicon layer, forming a well region, and forming a source region. The well region can be formed with a ?p-well implant. The source region can be performed with an n+ source implant.
    Type: Application
    Filed: August 26, 2011
    Publication date: December 22, 2011
    Inventors: Joseph A. Yedinak, Nathan L. Kraft
  • Publication number: 20110312166
    Abstract: Methods of manufacturing power semiconductor devices include forming an epitaxial and dielectric layer, patterning and etching the dielectric layer, forming a first oxide layer, forming a first conductive layer on top of the first oxide layer, etching the first conductive layer away inside an active trench, forming a second oxide layer and second conductive layer. The second conductive layer does not extend completely over the first conductive layer in a first region outside of the active trench. The methods further include forming a third oxide layer over the second conductive layer, etching a first opening through the third oxide layer exposing the second conductive layer outside the active trench, etching a second opening through the second oxide layer outside the active trench in the first region exposing the first conductive layer but not the second conductive layer, and filling the first and second openings with conductive material.
    Type: Application
    Filed: August 26, 2011
    Publication date: December 22, 2011
    Inventors: Joseph A. Yedinak, Nathan L. Kraft, Christopher B. Kocon, Richard Stokes
  • Patent number: 8043913
    Abstract: A method of forming a field effect transistor includes: forming a trench in a semiconductor region; forming a shield electrode in the trench; performing an angled sidewall implant of impurities of the first conductivity type to form a channel enhancement region adjacent the trench; forming a body region of a second conductivity type in the semiconductor region; and forming a source region of the first conductivity type in the body region, the source region and an interface between the body region and the semiconductor region defining a channel region therebetween, the channel region extending along the trench sidewall. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: October 25, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
  • Patent number: 8013391
    Abstract: A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, active trenches extending through the well region and into the drift region where the active trenches define an active area. Inside each of the active trenches is formed a first conductive gate electrode disposed along and insulated from a first trench sidewall, a second conductive gate electrode disposed along and insulated from a second trench sidewall, and a conductive shield electrode disposed between the first and second conductive gate electrodes, wherein the shield electrode is insulated from and extends deeper inside the trench than the first and second conductive gate electrodes. The device also includes source regions having the first conductivity type formed inside the well region and adjacent the active trenches.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: September 6, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Nathan L. Kraft
  • Patent number: 8013387
    Abstract: A semiconductor power device includes active trenches that define an active area and an edge area that is located outside of the active area. The active trenches include a lower shield poly, an upper gate poly, a first oxide layer and a second oxide layer wherein the first oxide layer separates the lower shield poly from the upper gate poly and the second oxide layer covers the upper gate poly. The lower shield poly, upper gate poly, first oxide layer and second oxide layer conform to the shapo of the active trench and extend from the active trench to a surface of the edge area. The edge area includes a first opening that extends through the first oxide layer to the lower shield poly and a second opening that extends through the second oxide layer to the upper gate poly.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: September 6, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Nathan L. Kraft, Christopher B. Kocon, Richard Stokes
  • Publication number: 20110177662
    Abstract: A method of forming a field effect transistor includes: forming a trench in a semiconductor region; forming a shield electrode in the trench; performing an angled sidewall implant of impurities of the first conductivity type to form a channel enhancement region adjacent the trench; forming a body region of a second conductivity type in the semiconductor region; and forming a source region of the first conductivity type in the body region, the source region and an interface between the body region and the semiconductor region defining a channel region therebetween, the channel region extending along the trench sidewall. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region.
    Type: Application
    Filed: March 29, 2011
    Publication date: July 21, 2011
    Inventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
  • Patent number: 7923776
    Abstract: A field effect transistor includes a body region of a first conductivity type in a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminating within the semiconductor region. A source region of the second conductivity type extends in the body region adjacent the gate trench. The source region and an interface between the body region and the semiconductor region define a channel region therebetween which extends along the gate trench sidewall. A channel enhancement region of the second conductivity type is formed adjacent the gate trench. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: April 12, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
  • Publication number: 20100258862
    Abstract: A field effect transistor includes a body region of a first conductivity type in a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminating within the semiconductor region. A source region of the second conductivity type extends in the body region adjacent the gate trench. The source region and an interface between the body region and the semiconductor region define a channel region therebetween which extends along the gate trench sidewall. A channel enhancement region of the second conductivity type is formed adjacent the gate trench. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region.
    Type: Application
    Filed: February 2, 2010
    Publication date: October 14, 2010
    Inventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
  • Publication number: 20090230465
    Abstract: A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.
    Type: Application
    Filed: March 16, 2009
    Publication date: September 17, 2009
    Inventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
  • Patent number: 7504303
    Abstract: A method for forming a shielded gate field effect transistor includes the following steps. Trenches extending into a silicon region are formed using a mask that includes a protective layer. A shield dielectric layer lining sidewalls and bottom of each trench is formed. A shield electrode is formed in a bottom portion of each trench. Protective spacers are formed along upper sidewalls of each trench. An inter-electrode dielectric is formed over the shield electrode. The protective spacers and the protective layer of the mask prevent formation of inter-electrode dielectric along the upper sidewalls of each trench and over mesa surfaces adjacent each trench. A gate electrode is formed in each trench over the inter-electrode dielectric.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: March 17, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
  • Publication number: 20090008706
    Abstract: A semiconductor power device includes active trenches that define an active area and an edge area that is located outside of the active area. The active trenches include a lower shield poly, an upper gate poly, a first oxide layer and a second oxide layer wherein the first oxide layer separates the lower shield poly from the upper gate poly and the second oxide layer covers the upper gate poly. The lower shield poly, upper gate poly, first oxide layer and second oxide layer conform to the shape of the active trench and extend from the active trench to a surface of the edge area. The edge area includes a first opening that extends through the first oxide layer to the lower shield poly and a second opening that extends through the second oxide layer to the upper gate poly. The first opening is filled with a conductive material that makes electrical contact with the lower shield poly and the second opening is filled with conductive material that makes electrical contact with the upper gate poly.
    Type: Application
    Filed: December 26, 2007
    Publication date: January 8, 2009
    Inventors: Joseph A. Yedinak, Nathan L. Kraft, Christopher B. Kocon, Richard Stokes
  • Publication number: 20090008709
    Abstract: A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, active trenches extending through the well region and into the drift region where the active trenches define an active area. Inside each of the active trenches is formed a first conductive gate electrode disposed along and insulated from a first trench sidewall, a second conductive gate electrode disposed along and insulated from a second trench sidewall, and a conductive shield electrode disposed between the first and second conductive gate electrodes, wherein the shield electrode is insulated from and extends deeper inside the trench than the first and second conductive gate electrodes. The device also includes source regions having the first conductivity type formed inside the well region and adjacent the active trenches.
    Type: Application
    Filed: December 21, 2007
    Publication date: January 8, 2009
    Inventors: Joseph A. Yedinak, Nathan L. Kraft
  • Patent number: 7416948
    Abstract: A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductivity type into the semiconductor region through an upper surface of the semiconductor region and through upper trench sidewalls not covered by the one or more material. A high temperature process is carried out to drive the implanted dopants deeper into the mesa region thereby forming body regions of the second conductivity type between adjacent trenches. Source regions of the first conductivity type are then formed in each body region.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: August 26, 2008
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Nathan L. Kraft, Ashok Challa, Steven P. Sapp, Hamza Yilmaz, Daniel Calafut, Dean E. Probst, Rodney S. Ridley, Thomas E. Grebs, Christopher B. Kocon, Joseph A. Yedinak, Gary M. Dolny