Patents by Inventor Naveen SUDA

Naveen SUDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230376745
    Abstract: A mechanism to control the stability and performance of weight-sharing methods for designing neural networks is provided. Network weights and architecture parameters of a super-net, including multiple sub-networks, are adjusted to reduce a loss determined, at least in part, from a sum, over layers of the sub-network, of measures of smoothness based on network weights in the layers. A sub-network of the super-net is selected dependent upon the adjusted architectural parameters.
    Type: Application
    Filed: May 23, 2022
    Publication date: November 23, 2023
    Applicant: Arm Limited
    Inventors: Kartikeya Bhardwaj, Guihong Li, Naveen Suda, Milos Milosavljevic, Danny Daysang Loh
  • Publication number: 20230196093
    Abstract: Disclosed is a novel neural network architecture and methods for generating neural network-based models from such architecture. A first version of the neural network, that is used for training purposes, includes one or more blocks in a first format that can then be replaced with corresponding blocks in a second format for execution. An executable model can thus be provided comprising a second version of the neural network including the one or more blocks in the second format. This then allows the training to be performed in a first, e.g. expanded format, but with a second, e.g. reduced, format model then provided for execution.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Applicant: Arm Limited
    Inventors: Kartikeya Bhardwaj, Naveen Suda, Lingchuan Meng, Alexander Eugene Chalfin, Danny Daysang Log
  • Patent number: 11636316
    Abstract: Broadly speaking, the present techniques exploit the properties of correlated electron materials for artificial neural networks and neuromorphic computing. In particular, the present techniques provide apparatuses/devices that comprise at least one correlated electron switch (CES) element and which may be used as, or to form, an artificial neuron or an artificial synapse.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 25, 2023
    Assignee: Cerfe Labs, Inc.
    Inventors: Lucian Shifren, Shidhartha Das, Naveen Suda, Carlos Alberto Paz de Araujo
  • Patent number: 11620516
    Abstract: The present disclosure advantageously provides a heterogenous system, and a method for generating an artificial neural network (ANN) for a heterogenous system. The heterogenous system includes a plurality of processing units coupled to a memory configured to store an input volume. The plurality of processing units includes first and second processing units. The first processing unit includes a first processor and is configured to execute a first ANN, and the second processing unit includes a second processor and is configured to execute a second ANN. The first and second ANNs respectively include an input layer, at least one processor-optimized hidden layer and an output layer. The second ANN hidden layers are different than the first ANN hidden layers.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: April 4, 2023
    Assignee: Arm Limited
    Inventors: Danny Daysang Loh, Lingchuan Meng, Naveen Suda, Eric Kunze, Ahmet Fatih Inci
  • Publication number: 20210192337
    Abstract: The present disclosure advantageously provides a heterogenous system, and a method for generating an artificial neural network (ANN) for a heterogenous system. The heterogenous system includes a plurality of processing units coupled to a memory configured to store an input volume. The plurality of processing units includes first and second processing units. The first processing unit includes a first processor and is configured to execute a first ANN, and the second processing unit includes a second processor and is configured to execute a second ANN. The first and second ANNs respectively include an input layer, at least one processor-optimized hidden layer and an output layer. The second ANN hidden layers are different than the first ANN hidden layers.
    Type: Application
    Filed: December 23, 2019
    Publication date: June 24, 2021
    Applicant: Arm Limited
    Inventors: Danny Daysang Loh, Lingchuan Meng, Naveen Suda, Eric Kunze, Ahmet Fatih Inci
  • Patent number: 10922608
    Abstract: Broadly speaking, embodiments of the present technique provide a neuron for a spiking neural network, where the neuron is formed of at least one Correlated Electron Random Access Memory (CeRAM) element or Correlated Electron Switch (CES) element.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: February 16, 2021
    Assignee: ARM LTD
    Inventors: Naveen Suda, Vikas Chandra, Brian Tracy Cline, Saurabh Pijuskumar Sinha, Shidhartha Das
  • Publication number: 20190236441
    Abstract: Broadly speaking, the present techniques exploit the properties of correlated electron materials for artificial neural networks and neuromorphic computing. In particular, the present techniques provide apparatuses/devices that comprise at least one correlated electron switch (CES) element and which may be used as, or to form, an artificial neuron or an artificial synapse.
    Type: Application
    Filed: January 31, 2018
    Publication date: August 1, 2019
    Inventors: Lucian SHIFREN, Shidhartha DAS, Naveen SUDA, Carlos Alberto PAZ de ARAUJO
  • Publication number: 20180260696
    Abstract: Broadly speaking, embodiments of the present technique provide a neuron for a spiking neural network, where the neuron is formed of at least one Correlated Electron Random Access Memory (CeRAM) element or Correlated Electron Switch (CES) element.
    Type: Application
    Filed: March 8, 2017
    Publication date: September 13, 2018
    Applicant: ARM LTD
    Inventors: Naveen SUDA, Vikas CHANDRA, Brian Tracy CLINE, Saurabh Pijuskumar SINHA, Shidhartha DAS