Patents by Inventor Navneeth Kankani
Navneeth Kankani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9639463Abstract: The various implementations described herein include systems, methods and/or devices used to enable heuristic aware garbage collection in storage systems (e.g., non-volatile data storage systems using one or more flash memory devices). In one aspect, a time parameter (e.g., dwell time) and/or heuristics (e.g., error count, error rate, number of reads, number of times programmed, etc.) are used in a garbage collection scheme. For example, in some implementations, the method of garbage collection for a storage medium in a storage system includes (1) determining a time parameter for a block in the storage medium, and (2) in accordance with a determination that the time parameter for the block is greater than a first threshold time, enabling garbage collection of the block.Type: GrantFiled: September 17, 2013Date of Patent: May 2, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Navneeth Kankani, Anand Kulkarni, Charles See Yeung Kwong
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Patent number: 9606737Abstract: Systems, methods, and/or devices are used to implement variable bit encoding per NAND flash cell to extend life of flash-based storage devices and preserve over-provisioning. In some embodiments, the method includes detecting a trigger condition with respect to one or more non-volatile memory portions (e.g., portions configured to store data encoded in a first encoding format and having a first storage density) of a plurality of non-volatile memory portions of a storage device. In response to detecting the trigger condition and in accordance with a first determination that a projected amount of over-provisioning (e.g., corresponding to over-provisioning for the storage device after reconfiguring the one or more non-volatile memory portions to store data encoded in a second encoding format and having a second storage density) meets predefined over-provisioning criteria, the method includes reconfiguring the one or more non-volatile memory portions to store data encoded in the second encoding format.Type: GrantFiled: October 30, 2015Date of Patent: March 28, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Navneeth Kankani, Linh Tien Truong
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Publication number: 20160342345Abstract: Systems, methods, and/or devices are used to implement variable bit encoding to improve device endurance and extend life of storage devices. In some embodiments, the method includes detecting a trigger condition with respect to one or more non-volatile memory portions (e.g., portions configured to store data encoded in a first encoding format) of a plurality of non-volatile memory portions of a storage device. In accordance with detecting the trigger condition, the method includes: determining a current and an estimated endurance metric for the plurality of non-volatile memory portions (e.g., corresponding to estimated endurance after reconfiguration of the one or more portions to store data encoded in a second encoding format), and in accordance with a determination that reconfiguration criteria are satisfied (e.g., the estimated endurance metric comprises an improvement over the current endurance metric), reconfiguring the one or more portions to store data encoded in the second encoding format.Type: ApplicationFiled: October 30, 2015Publication date: November 24, 2016Inventors: Navneeth Kankani, Linh Tien Truong
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Publication number: 20160342344Abstract: Systems, methods, and/or devices are used to implement variable bit encoding per NAND flash cell to extend life of flash-based storage devices and preserve over-provisioning. In some embodiments, the method includes detecting a trigger condition with respect to one or more non-volatile memory portions (e.g., portions configured to store data encoded in a first encoding format and having a first storage density) of a plurality of non-volatile memory portions of a storage device. In response to detecting the trigger condition and in accordance with a first determination that a projected amount of over-provisioning (e.g., corresponding to over-provisioning for the storage device after reconfiguring the one or more non-volatile memory portions to store data encoded in a second encoding format and having a second storage density) meets predefined over-provisioning criteria, the method includes reconfiguring the one or more non-volatile memory portions to store data encoded in the second encoding format.Type: ApplicationFiled: October 30, 2015Publication date: November 24, 2016Inventors: Navneeth Kankani, Linh Tien Truong
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Patent number: 9361221Abstract: The various implementations described herein include systems, methods and/or devices used to enable write amplification reduction through reliable writes during garbage collection. In one aspect, lower page/upper page programming is used during write operations performed in response to a host command and coarse/fine programming is used during garbage collection.Type: GrantFiled: September 17, 2013Date of Patent: June 7, 2016Assignee: SANDISK TECHNOLOGIES INC.Inventors: Navneeth Kankani, Charles See Yeung Kwong
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Patent number: 9244763Abstract: The various implementations described herein include systems, methods and/or devices that may enhance the reliability with which data can be stored in and read from a memory. The method includes obtaining symbol transition information corresponding to symbol read errors identified while reading data from flash memory cells in a flash memory device. The method further includes determining a reading threshold voltage offset, based at least in part on: a plurality of probability values determined from the symbol transition information; a current count of program-erase cycles; and a word line zone value for a word line zone containing the flash memory cells. Additionally, the method includes generating an updated reading threshold voltage in accordance with the reading threshold voltage offset and the current value of the reading threshold voltage.Type: GrantFiled: September 17, 2013Date of Patent: January 26, 2016Assignee: SANDISK ENTERPRISE IP LLCInventors: Navneeth Kankani, Charles See Yeung Kwong
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Patent number: 9235509Abstract: The various implementations described herein include systems, methods and/or devices used to enable write amplification reduction by delaying read access to data written during garbage collection. In one aspect, read access to a write unit to which data was written during garbage collection is delayed until a predefined subsequent operation has been completed.Type: GrantFiled: September 17, 2013Date of Patent: January 12, 2016Assignee: SANDISK ENTERPRISE IP LLCInventors: Navneeth Kankani, Charles See Yeung Kwong
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Publication number: 20150347229Abstract: A memory controller configures a plurality of word lines associated with a respective block of a 3D memory device in a first configuration, where the first configuration includes a set of configuration parameters for each word line of the plurality of word lines determined at least in part on the vertical positions of each word line relative to a substrate of the 3D memory device and, while the plurality of word lines are configured in the first configuration, writes data to and reads data from the respective block. For the respective block, the memory controller: adjusts a first parameter in the respective set of configuration parameters corresponding to a respective word line of the plurality of word lines in response to detecting a first trigger condition as to the respective word line and, after adjusting the first parameter, writes data to and reads data from the respective word line.Type: ApplicationFiled: November 17, 2014Publication date: December 3, 2015Inventors: James M. Higgins, Robert W. Ellis, Neil R. Darragh, Aaron K. Olbrich, Navneeth Kankani, Steven Sprouse
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Publication number: 20150347039Abstract: A storage system includes a memory controller and a storage device with one or more memory devices, each with a plurality of memory portions. The memory controller determines an initial storage capacity for each of the one or more memory devices, where the one or more memory devices are configured in a first storage density. The memory controller detects a trigger condition as to at least one memory portion of a respective device of the one or more memory devices and, in response to detecting the trigger condition, recharacterizes the at least one memory portion of the respective memory device so as to be configured in a second storage density, where the at least one recharacterized memory portion of the respective memory device has a reduced storage capacity. After the recharacterizing, the memory controller determines a revised storage capacity for the respective memory device.Type: ApplicationFiled: July 1, 2014Publication date: December 3, 2015Inventors: Linh Tien Truong, Allen Samuels, Navneeth Kankani
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Patent number: 9164830Abstract: A first data set is written to first memory units identified as having a higher data reliability and a second data set is written to second memory units identified as having a lower data reliability than the first memory units. In some cases, the second data set may include metadata or redundancy information that is useful to aid in reading and/or decoding the first data set. The act of writing the second data set increases the data reliability of the first data set. The second data set may be a null pattern, such as all erased bits.Type: GrantFiled: January 14, 2014Date of Patent: October 20, 2015Assignee: SEAGATE TECHNOLOGY LLCInventors: Navneeth Kankani, Mark Allen Gaertner, Rodney Virgil Bowman, Ryan James Goss, David Scott Seekins, Tong Shirh Stone
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Patent number: 9037624Abstract: The disclosure is related systems and methods for using operation durations of a data storage medium to generate random numbers. In one embodiment, a device may comprise a random number generator circuit configured to store a value representing a duration of an operation on the data storage medium, and generate a random number based on the value. Another embodiment may be a method comprising recording durations of access operations to a data storage medium, and generating a random number based on the durations.Type: GrantFiled: August 3, 2012Date of Patent: May 19, 2015Assignee: Seagate Technology LLCInventors: Laszlo Hars, Monty Aaron Forehand, Donald Preston Matthews, Tong Shirh Stone, Navneeth Kankani, Rodney Virgil Bowman
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Patent number: 8891303Abstract: A memory controller configures a plurality of word lines associated with a respective block of a 3D memory device in a first configuration, where the first configuration includes a set of configuration parameters for each word line of the plurality of word lines determined at least in part on the vertical positions of each word line relative to a substrate of the 3D memory device and, while the plurality of word lines are configured in the first configuration, writes data to and reads data from the respective block. For the respective block, the memory controller: adjusts a first parameter in the respective set of configuration parameters corresponding to a respective word line of the plurality of word lines in response to detecting a first trigger condition as to the respective word line and, after adjusting the first parameter, writes data to and reads data from the respective word line.Type: GrantFiled: June 6, 2014Date of Patent: November 18, 2014Assignee: Sandisk Technologies Inc.Inventors: James M. Higgins, Robert W. Ellis, Neil R. Darragh, Aaron K. Olbrich, Navneeth Kankani, Steven Sprouse
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Patent number: 8806106Abstract: Completion times of data storage operations targeted to a non-volatile, solid-state memory device are measured. Wear of the memory device is estimated using the measured completion times, and life cycle management operations are performed to affect subsequent wear of the memory device in accordance with the estimated wear. The life cycle management may include operations such as wear leveling, predicting an end of service life of the memory device, and removing worn blocks of the memory device from service.Type: GrantFiled: November 12, 2010Date of Patent: August 12, 2014Assignee: Seagate Technology LLCInventors: Ryan James Goss, David Scott Seekins, David Scott Ebsen, Navneeth Kankani
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Publication number: 20140129891Abstract: A first data set is written to first memory units identified as having a higher data reliability and a second data set is written to second memory units identified as having a lower data reliability than the first memory units. In some cases, the second data set may include metadata or redundancy information that is useful to aid in reading and/or decoding the first data set. The act of writing the second data set increases the data reliability of the first data set. The second data set may be a null pattern, such as all erased bits.Type: ApplicationFiled: January 14, 2014Publication date: May 8, 2014Applicant: Seagate Technology LLCInventors: Navneeth Kankani, Mark Allen Gaertner, Rodney Virgil Bowman, Ryan James Goss, David Scott Seekins, Tong Shirh Stone
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Patent number: 8705291Abstract: Method and apparatus for sanitizing a non-volatile memory, such as a flash memory array. In accordance with various embodiments, a memory cell is sanitized by using a write circuit to accumulate charge on a floating gate of the cell to a level such that application of a maximum available read sensing voltage to a control gate of the cell is insufficient to place the cell in a conductive state.Type: GrantFiled: May 27, 2011Date of Patent: April 22, 2014Assignee: Seagate Technology LLCInventors: Ryan James Goss, David Scott Seekins, Navneeth Kankani
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Patent number: 8631294Abstract: A first data set is written to first memory units identified as having a higher data reliability and a second data set is written to second memory units identified as having a lower data reliability than the first memory units. In some cases, the second data set may include metadata or redundancy information that is useful to aid in reading and/or decoding the first data set. The act of writing the second data set increases the data reliability of the first data set. The second data set may be a null pattern, such as all erased bits.Type: GrantFiled: February 2, 2011Date of Patent: January 14, 2014Assignee: Seagate Technology LLCInventors: Navneeth Kankani, Mark A. Gaertner, Rodney V. Bowman, Ryan J. Goss, David S. Seekins, Tong Shirh Stone
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Publication number: 20120300554Abstract: Method and apparatus for sanitizing a non-volatile memory, such as a flash memory array. In accordance with various embodiments, a memory cell is sanitized by using a write circuit to accumulate charge on a floating gate of the cell to a level such that application of a maximum available read sensing voltage to a control gate of the cell is insufficient to place the cell in a conductive state.Type: ApplicationFiled: May 27, 2011Publication date: November 29, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: Ryan James Goss, David Scott Seekins, Navneeth Kankani
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Publication number: 20120198312Abstract: A first data set is written to first memory units identified as having a higher data reliability and a second data set is written to second memory units identified as having a lower data reliability than the first memory units. In some cases, the second data set may include metadata or redundancy information that is useful to aid in reading and/or decoding the first data set. The act of writing the second data set increases the data reliability of the first data set. The second data set may be a null pattern, such as all erased bits.Type: ApplicationFiled: February 2, 2011Publication date: August 2, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: Navneeth Kankani, Mark Allen Gaertner, Rodney Virgil Bowman, Ryan James Goss, David Scott Seekins, Tong Shirh Stone
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Publication number: 20120124273Abstract: Completion times of data storage operations targeted to a non-volatile, solid-state memory device are measured. Wear of the memory device is estimated using the measured completion times, and life cycle management operations are performed to affect subsequent wear of the memory device in accordance with the estimated wear. The life cycle management may include operations such as wear leveling, predicting an end of service life of the memory device, and removing worn blocks of the memory device from service.Type: ApplicationFiled: November 12, 2010Publication date: May 17, 2012Applicant: Seagate Technology LLCInventors: Ryan J. Goss, David Scott Seekins, David Scott Ebsen, Navneeth Kankani