Abstract: A variable attenuator and method of attenuating a signal is presented. The variable attenuator contains an input that receives an input signal to be attenuated. A voltage divider between a resistor and parallel MOSFETs provides the attenuated input signal. The MOSFETs have different sizes and have gates that are connected to a control signal through different resistances such that the larger the MOSFET, the larger the resistance. The control signal is dependent on the output of the attenuator. The arrangement extends the linearity of the attenuation over a wide voltage range of the control signal and decreases the intermodulation distortion of the attenuator.

Abstract: A direct digital synthesis circuit (108) includes a plurality of current sources (210, 211, 212), an output circuit (200), and a logical multiplier circuit (202). The output circuit (200) provides a synthesized waveform (164) output and includes a first (206) and second branch (208). The logical multiplier circuit (202) is operatively coupled to the plurality of current sources (210, 211, 212) and to the output circuit (200). The logical multiplier circuit (202) is operative to receive a plurality of signals. The logical multiplier circuit is also operative to selectively increase a first current flow through the first branch (206) by a determined magnitude and decrease a second current flow through the second branch (208) by the determined magnitude based on the plurality of signals. The synthesized waveform (164) is based on the first and second currents.

Abstract: A variable attenuator and method of attenuating a signal is presented. The variable attenuator contains an input that receives an input signal to be attenuated. A voltage divider between a resistor and parallel MOSFETs provides the attenuated input signal. The MOSFETs have different sizes and have gates that are connected to a control signal through different resistances such that the larger the MOSFET, the larger the resistance. The control signal is dependent on the output of the attenuator. The arrangement extends the linearity of the attenuation over a wide voltage range of the control signal and decreases the intermodulation distortion of the attenuator.

Abstract: A variable attenuator and method of attenuating a signal is presented. The variable attenuator contains an input that receives an input signal to be attenuated. A voltage divider between a resistor and parallel MOSFETs provides the attenuated input signal. The MOSFETs have different sizes and have gates that are connected to a control signal through different resistances such that the larger the MOSFET, the larger the resistance. The control signal is dependent on the output of the attenuator. The arrangement extends the linearity of the attenuation over a wide voltage range of the control signal and decreases the intermodulation distortion of the attenuator.

Abstract: A dual mode voltage supply circuit (50) includes an active mode voltage supply circuit (58) and a passive mode voltage supply circuit (60). The active mode voltage supply circuit (58) is selectively operative to supply a voltage (57) based on mode control information (22). The active mode voltage supply circuit (58) is operative to provide a first current capacity. The passive mode voltage supply circuit (60) is operatively coupled to the active mode voltage supply circuit (58). The passive mode voltage supply circuit (60) is operative to supply the voltage (57) when the active mode voltage supply circuit (58) is not supplying the voltage (57). The passive mode voltage supply circuit (60) is operative to provide a second current capacity that is less than the first current capacity.

Abstract: An amplifier, tuner, and method of amplification are provided. The amplifier has a pair of transistors. Each transistor has a control terminal and an output terminal disposed between the transistor and a power supply input. A first network is connected between each power supply input and output terminal. The first network contains a first resistor and a first switch connected in parallel with the first resistor. A second network is connected between the transistors. The second network contains a first and second combination. Each of the first and second combinations contains a second resistor and a second switch connected in parallel with the second resistor. The first and second combinations are connected by a third switch.

Abstract: An edge seal structure and fabrication method are described. The edge seal structure includes a high impedance substrate containing a base material and a grounded floating edge seal that is on the substrate but is isolated from the base material. The edge seal contacts a first doped well in the substrate that has the same conductivity type as and is more heavily doped than the base material. The first doped well is in a second doped well that has a different conductivity type than the first doped well. The first and second doped wells and the base material form back-to-back series connected diodes. The wells are effectively connected to power and ground such that the diodes are reverse-biased. The edge seal is formed by a stack of conductive layers, at least some of which are surrounded by a stack of insulating layers.

Abstract: A direct digital synthesis circuit (108) includes a plurality of current sources (210, 211, 212), an output circuit (200), and a logical multiplier circuit (202). The output circuit (200) provides a synthesized waveform (164) output and includes a first (206) and second branch (208). The logical multiplier circuit (202) is operatively coupled to the plurality of current sources (210, 211, 212) and to the output circuit (200). The logical multiplier circuit (202) is operative to receive a plurality of signals. The logical multiplier circuit is also operative to selectively increase a first current flow through the first branch (206) by a determined magnitude and decrease a second current flow through the second branch (208) by the determined magnitude based on the plurality of signals. The synthesized waveform (164) is based on the first and second currents.

Abstract: A dual mode voltage supply circuit (50) includes an active mode voltage supply circuit (58) and a passive mode voltage supply circuit (60). The active mode voltage supply circuit (58) is selectively operative to supply a voltage (57) based on mode control information (22). The active mode voltage supply circuit (58) is operative to provide a first current capacity. The passive mode voltage supply circuit (60) is operatively coupled to the active mode voltage supply circuit (58). The passive mode voltage supply circuit (60) is operative to supply the voltage (57) when the active mode voltage supply circuit (58) is not supplying the voltage (57). The passive mode voltage supply circuit (60) is operative to provide a second current capacity that is less than the first current capacity.

Abstract: A regulation circuit, incorporated in a single integrated circuit with a first circuit load, which as an input coupled to a power supply which produces a source voltage, and a first output coupled to the first circuit load. The regulation circuit comprises an input capacitor for reducing the magnitude of a voltage change at the first output, and at least a first voltage regulator for producing a predetermined voltage at the first load.

Abstract: A high gain wide-band width RF amplifier 120 with automatic bias supply regulation. The load supply is actively adjusted in response to the amplifier's output signal level. At small output signals effective load supply voltage is minimum and at larger output signals the effective load supply voltages is maximized. The amplifier 120 includes a differential pair of field effect transistors (FETs) 102, 104 connected at common source connection 106 and biased by current bias FET 108 which is connected between common source connection 106 and amplifier signal input RFIN. A bias voltage (VB1) is applied to the gate of bias device 108 and an automatic gain control voltage (VAGC) is applied to the gates of differential FET pair 102, 104. The automatic bias supply circuit 122 is an active load and includes resistors 124, 126, capacitor 128 and a differential amplifier 130. Capacitor 128 is connected between the negative input 132 and the output 134 of differential amplifier 130.

Abstract: A high gain wide-band width RF amplifier 120 with automatic bias supply regulation. The load supply is actively adjusted in response to the amplifier's output signal level. At small output signals effective load supply voltage is minimum and at larger output signals the effective load supply voltages is maximized. The amplifier 120 includes a differential pair of field effect transistors (FETs) 102, 104 connected at common source connection 106 and biased by current bias FET 108 which is connected between common source connection 106 and amplifier signal input RFIN. A bias voltage (VB1) is applied to the gate of bias device 108 and an automatic gain control voltage (VAGC) is applied to the gates of differential FET pair 102, 104. The automatic bias supply circuit 122 is an active load and includes resistors 124, 126, capacitor 128 and a differential amplifier 130. Capacitor 128 is connected between the negative input 132 and the output 134 of differential amplifier 130.

Abstract: A single ended input differential output amplifier (100) and integrated circuit including such an amplifier (100). A pair of load resistors (102, 104) are connected between a supply voltage (Vdd) and differential outputs OUTP and OUTM. An inductor (106) is connected between input RFIN and a source bias voltage VBS. A first field effect transistor (FET) (108) is connected, drain to source, between load resistor (102) at output OUTP and inductor (106) at RFIN. A second FET (110) is connected, drain to source, between the second load resistor (104) at output OUTM and the source bias voltage VBS. A gate bias voltage VBg is connected to the gate of FET (108) and through resistor (112) to the gate of FET (110). A coupling capacitor (114) is connected between the input RFIN and the gate of FET (110).

Abstract: A regulation circuit, incorporated in a single integrated circuit with a first circuit load, which as an input coupled to a power supply which produces a source voltage, and a first output coupled to the first circuit load. The regulation circuit comprises an input capacitor for reducing the magnitude of a voltage change at the first output, and at least a first voltage regulator for producing a predetermined voltage at the first load.

Abstract: A single ended input differential output amplifier (100) and integrated circuit including such an amplifier (100). A pair of load resistors (102, 104) are connected between a supply voltage (Vdd) and differential outputs OUTP and OUTM. An inductor (106) is connected between input RFIN and a source bias voltage VBs. A first field effect transistor (FET) (108) is connected, drain to source, between load resistor (102) at output OUTP and inductor (106) at RFIN. A second FET (110) is connected, drain to source, between the second load resistor (104) at output OUTM and the source bias voltage VBS. A gate bias voltage VBg is connected to the gate of FET (108) and through resistor (112) to the gate of FET (110). A coupling capacitor (114) is connected between the input RFIN and the gate of FET (110).

Abstract: A circuit (34) for data recovery in a wireless powered communication device (10) obviates the need for the costly high power consumption filters of prior art devices by deriving a clock signal from the power coil (18), and then sampling the data coil (20) signal with the derived sampling clock. The step of deriving a clock signal from the power signal causes the component of the power signal present on the data signal to be aliased to DC which is then easily rejected with a low order high pass or bandpass filter (38). Furthermore, the data signal may be amplified to a desired level suitable for amplitude discrimination by a simple comparator circuit (40) with hysteresis. Demodulation of the data signal is easily accomplished in the digital domain using a digital demodulator (32).

Abstract: The present invention expands the range over which a wireless powered communication device (500) and device reader (12) can communicate. In the present invention, circuitry (502) within the device (500) provides for determining a characteristic of the received communication signal. Based upon this signal characteristic data recovery parameters are adapted to enhance data recovery over a maximize communication distance. In a preferred embodiment of the present invention, the magnitude of the power signal is observed. It is known that the power signal varies as an inverse square of the distance of the device (500) to the reader. From this information, a data detection threshold is adjusted to enhance data recovery.

Abstract: An interference dependent adaptive phase clock controller method and system includes synthesis of a signal processing clock signal (307). An interference signal (311 ) dependent on a phase of the signal processing clock signal is measured, and a phase correction signal (317) is provided dependent thereon. A magnitude of the interference signal is reduced by adjusting the phase of the signal processing clock signal (307) dependent on the phase correction signal (317).

Abstract: A low voltage differential amplifier 10 or comparator is accomplished by providing an differential amplifier 10 that includes a transistor bias simulator 32 and a capacitance circuit 36. The transistor bias simulator 32 matches the gate to source bias voltage of the load transistor 22 and provides this value to the capacitance circuit 36. The capacitance circuit 36, which is coupled to a biasing reference voltage 38, charges a capacitor 84 based on the difference between the biasing reference voltage 38 and the simulated bias voltage 34. This charged capacitor 86 is used during an auto-zeroing phase to bias the drain to source voltage of the load transistor 22 to a state at which it is just beyond the onset of saturation.

Abstract: A diagnostic system for measuring behavior of signals provided by a plurality of sensors (101, 129) includes a plurality of input filters (107, 135) for receiving signals (105, 133) from each of the plurality of sensors (103, 131) and for providing a plurality of filtered sensor signals (109, 137) each derived from the received signals (105, 133). A signal bandwidth of each of the plurality of filtered sensor signals (109, 137) is lower than a signal bandwidth of the than a signal bandwidth of the associated received signal. A selection circuit (119) receives each of the signals (105, 133) from each of the plurality of sensors (103, 131) and, dependent on a selection signal (127), provides a selected sensor signal (121) derived from one of the received signals (105), wherein the selected sensor signal (121) has a signal bandwidth greater than one of the filtered sensor signals (109) derived from the one of the received signals (105).