Abstract: A radio frequency front end for a television band receiver and spectrum sensor includes a low noise amplifier that amplifies a received signal output of a radio frequency antenna connected to the radio frequency front end, a pin diode attenuator circuit that selectively attenuates an output of the low noise amplifier, and a buffer amplifier that amplifies an output of the pin diode attenuator.

Abstract: A spectrum sensor detects the presence of incumbent signals in the television-band. The spectrum sensor can detect digital Advanced Television Systems Committee (ATSC) signals below a ?114 dBm signal level and wireless microphone signals below a ?110 dBm signal level with false detection rates less than 10%. A radio module receives radio-frequency signals and produces an intermediate-frequency signal reflecting signal received in a selected television channel. A baseband processor module receives the intermediate-frequency signal, digitizes it, and processes the digital data to detecting whether an incumbent signal is present in the selected channel. The processing may include using pilot detection based on power spectrum thresholding or statistic characteristic extraction to detect ATSC signals. The processing may also include using power spectrum thresholding or covariance based signal detection to detect wireless microphone signals.

Abstract: A radio frequency front end for a television band receiver and spectrum sensor includes a first plurality of adaptive matching networks connected to a signal summer that combines signals received by the first plurality of antennas respectively connected to the first plurality of adaptive matching networks and outputs a combined signal to each of a second plurality of downconverter/tuners. The downconverter/tuners are respectively or collectively connected to an analog to digital converter that converts output of the second plurality of downconverter/tuners into at least one digital signal that is output to the television band receiver and spectrum sensor.

Abstract: A radio frequency front end for a television band receiver and spectrum sensor includes a low noise amplifier that amplifies a received signal output of a radio frequency antenna connected to the radio frequency front end, a pin diode attenuator circuit that selectively attenuates an output of the low noise amplifier, and a buffer amplifier that amplifies an output of the pin diode attenuator.

Abstract: The invention relates generally to the field of wireless communications and more particularly to a method of and device for detecting the presence of a received data packet in a digital receiver. The present invention proposes a simplified method of correlation by removing dependency on the amplitude fluctuations while at the same time maintaining phase relevancy. The key advancement involves mapping the complex quadrature amplitude modulation (QAM) preamble to a quantized phase shift keying (PSK) constellation before application to a matched complex correlator. The proposed process essentially “amplitude normalizes” the input signal without the use or complexity associated with a divider. This simplified normalization scheme makes the packet detection algorithm robust against amplitude variations in the input signal, while still allowing for good correlation output.

Abstract: A radio frequency front end for a television band receiver and spectrum sensor includes a first plurality of adaptive matching networks connected to a signal summer that combines signals received by the first plurality of antennas respectively connected to the first plurality of adaptive matching networks and outputs a combined signal to each of a second plurality of downconverter/tuners. The downconverter/tuners are respectively or collectively connected to an analog to digital converter that converts output of the second plurality of downconverter/tuners into at least one digital signal that is output to the television band receiver and spectrum sensor.

Abstract: The invention relates generally to the field of wireless communications and more particularly to a method of and device for detecting the presence of a received data packet in a digital receiver. The present invention proposes a simplified method of correlation by removing dependency on the amplitude fluctuations while at the same time maintaining phase relevancy. The key advancement involves mapping the complex quadrature amplitude modulation (QAM) preamble to a quantized phase shift keying (PSK) constellation before application to a matched complex correlator. The proposed process essentially “amplitude normalizes” the input signal without the use or complexity associated with a divider. This simplified normalization scheme makes the packet detection algorithm robust against amplitude variations in the input signal, while still allowing for good correlation output.

Abstract: The invention relates generally to the field of wireless communications and more particularly to a method of and device for detecting the presence of a received data packet in a digital receiver. The present invention proposes a simplified method of correlation by removing dependency on the amplitude fluctuations while at the same time maintaining phase relevancy. The key advancement involves mapping the complex quadrature amplitude modulation (QAM) preamble to a quantized phase shift keying (PSK) constellation before application to a matched complex correlator. The proposed process essentially “amplitude normalizes” the input signal without the use or complexity associated with a divider. This simplified normalization scheme makes the packet detection algorithm robust against amplitude variations in the input signal, while still allowing for good correlation output.

Abstract: A method of and device for automatic gain control (AGC) incorporates digitally controlled variable gain amplifiers (VGAs). An AGC circuit comprises multiple AGC stages, where each of the stages comprises: respective I and Q VGAs; a detector for detecting respective I and Q output signals received from the respective I and Q VGAs; an analogue to digital converter for converting the detected I and Q output signals; and a digital engine for adjusting the respective I and Q VGAs for differences between the detected I and Q output signals and a reference signal. Using staggered AGCs incorporating respective I and Q VGAs splits the total dynamic range between n stages, allowing for reduced gain requirements in the VGAs. Using digital control for setting the VGA gains reduces analogue variations and I/Q gain imbalances. Using multiple update rates or magnitudes in the VGA control improves dynamic settling time.

Abstract: A multi-channel RF receiver uses an image rejection mixer (e.g. double quadrature mixer) in the IF down conversion stage for image side band rejection (whereby use of an IF narrow band filter for image rejection may be omitted if desired) and comprises a simplified frequency synthesizer which generates both a “wandering” IF oscillator frequency and an RF oscillator frequency for the up/down conversion stages (being, for down conversion, from RF to IF and from IF to base band. The IF used for a particular RF carrier (channel) is selected so as to be both an integer (N) sub-harmonic of that RF carrier and within the operating frequency band of the image rejection mixer. Advantageously, the synthesizer comprises only one loop and one VCO, wherein the IF oscillator signal is produced from the RF oscillator signal by means of a frequency divider.

Abstract: A multi-channel RF receiver uses an image rejection mixer (e.g. double quadrature mixer) in the IF down conversion stage for image side band rejection (whereby use of an IF narrow band filter for image rejection may be omitted if desired) and comprises a simplified frequency synthesizer which generates both a “wandering” IF oscillator frequency and an RF oscillator frequency for the up/down conversion stages (being, for down conversion, from RF to IF and from IF to base band. The IF used for a particular RF carrier (channel) is selected so as to be both an integer (N) sub-harmonic of that RF carrier and within the operating frequency band of the image rejection mixer. Advantageously, the synthesizer comprises only one loop and one VCO, wherein the IF oscillator signal is produced from the RF oscillator signal by means of a frequency divider.

Abstract: A multi-channel RF receiver uses an image rejection mixer (e.g. double quadrature mixer) in the IF down conversion stage for image side band rejection (whereby use of an IF narrow band filter for image rejection may be omitted if desired) and comprises a simplified frequency synthesizer which generates both a “wandering” IF oscillator frequency and an RF oscillator frequency for the up/down conversion stages (being, for down conversion, from RF to IF and from IF to base band. The IF used for a particular RF carrier (channel) is selected so as to be both an integer (N) sub-harmonic of that RF carrier and within the operating frequency band of the image rejection mixer. Advantageously, the synthesizer comprises only one loop and one VCO, wherein the IF oscillator signal is produced from the RF oscillator signal by means of a frequency divider.

Abstract: A digital demodulator which coherently demodulates a low-IF or zero-IF complex signal using a complex-valued phase-locked loop (CPPL). The CPPL includes a numerical controlled oscillator, four multipliers and two combiners to provide independent phase/frequency and amplitude outputs. The CPLL exhibits in first order PLL dynamics without a loop filter in the feedback loop to the NCO. However a filter with one or more poles may be included in the feedback circuit to exhibit 2nd or higher order PLL dynamics. The CPLL allows coherent demodulation of extremely low FM modulation indexes whereby the incoming frequency drift may be larger than the frequency deviation. It can also be used to coherently demodulate signals which have combined amplitude and phase characteristics.

Abstract: A low power IF strip architecture suitable for Zero-IF (ZIF) or low-IF (LIF) radio receivers for filtering and amplifying a received signal. The apparatus includes a plurality of sequentially connected complex filter/amplifier stages. Each stage includes a complex filter having one or more poles and an automatic gain controlled amplifier (AGC). Each AGC may be feedback or feedforward with fixed minimum and maximum gains. Each stage further includes a control circuit that produces a gain control signal for controlling the amplifier gain within the fixed minimum and maximum gains as a function of a projected amplitude level. The received signal passes through multiple stages of filtering and controlled amplification to attenuate the interfering signal and amplify the desired signal. This is done at a restricted level in each stage such that the circuits in the stages operate at efficient power saving levels.

Abstract: The invention relates generally to the field of wireless communications and more particularly to a method of and device for detecting the presence of a received data packet in a digital receiver. The present invention proposes a simplified method of correlation by removing dependency on the amplitude fluctuations while at the same time maintaining phase relevancy. The key advancement involves mapping the complex quadrature amplitude modulation (QAM) preamble to a quantized phase shift keying (PSK) constellation before application to a matched complex correlator. The proposed process essentially “amplitude normalizes” the input signal without the use or complexity associated with a divider. This simplified normalization scheme makes the packet detection algorithm robust against amplitude variations in the input signal, while still allowing for good correlation output.

Abstract: The invention relates to the field of wireless communications, more particularly to a method of and device for automatic gain control (AGC) incorporating digitally controlled variable gain amplifiers (VGAs). The invention provides an AGC circuit comprising an I/Q baseband strip comprising multiple AGC stages wherein each of the AGC stages comprises: respective I and Q VGAs; a detector for detecting respective I and Q output signals received from the respective I and Q VGAs; an analogue to digital converter (ADC) for converting the detected I and Q output signals; and a digital engine for adjusting the respective I and Q VGAs for differences between the detected I and Q output signals and a reference signal. The use of staggered AGCs incorporating respective I and Q VGAs means that the total dynamic range is split between n-stages, thereby allowing for reduced gain requirements in the VGAs.

Abstract: A digital demodulator which coherently demodulates a low-IF or zero-IF complex signal using a complex-valued phase-locked loop (CPPL). The CPPL includes a numerical controlled oscillator, four multipliers and two combiners to provide independent phase/frequency and amplitude outputs. The CPLL exhibits in first order PLL dynamics without a loop filter in the feedback loop to the NCO. However a filter with one or more poles may be included in the feedback circuit to exhibit 2nd or higher order PLL dynamics. The CPLL allows coherent demodulation of extremely low FM modulation indexes whereby the incoming frequency drift may be larger than the frequency deviation. It can also be used to coherently demodulate signals which have combined amplitude and phase characteristics.

Abstract: A digital demodulator which coherently demodulates a low-IF or zero-IF complex signal using a complex-valued phase-locked loop (CPPL). The CPPL includes a numerical controlled oscillator, four multipliers and two combiners to provide independent phase/frequency and amplitude outputs. The CPLL exhibits in first order PLL dynamics without a loop filter in the feedback loop to the NCO. However a filter with one or more poles may be included in the feedback circuit to exhibit 2nd or higher order PLL dynamics. The CPLL allows coherent demodulation of extremely low FM modulation indexes whereby the incoming frequency drift may be larger than the frequency deviation. It can also be used to coherently demodulate signals which have combined amplitude and phase characteristics.

Abstract: Methods and devices relating to radio applications. An input signal with an input frequency is fed into a double quadrature mixer circuit along with a local oscillator signal with a local oscillator frequency. These two signals are multiplied by the mixer circuit and produces an output signal with a frequency substantially equal to either a sum of the local oscillator frequency and the input frequency or a difference of the local oscillator frequency and the input frequency. By using the quadrature mixer, the output signal consists mainly of only one sideband of the multiplication process. The carrier is mainly suppressed along with the other sideband. The output signal is particularly useful as a small frequency offset for a synthesized signal.

Abstract: A multi-channel RF receiver uses an image rejection mixer (e.g. double quadrature mixer) in the IF down conversion stage for image side band rejection (whereby use of an IF narrow band filter for image rejection may be omitted if desired) and comprises a simplified frequency synthesizer which generates both a “wandering” IF oscillator frequency and an RF oscillator frequency for the up/down conversion stages (being, for down conversion, from RF to IF and from IF to base band. The IF used for a particular RF carrier (channel) is selected so as to be both an integer (N) sub-harmonic of that RF carrier and within the operating frequency band of the image rejection mixer. Advantageously, the synthesizer comprises only one loop and one VCO, wherein the IF oscillator signal is produced from the RF oscillator signal by means of a frequency divider.