Patents by Inventor Nenad Pavlovic

Nenad Pavlovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10581439
    Abstract: Embodiments of a clock synchronization unit of an All Digital Phase-Locked Loop (ADPLL), a successive approximation register (SAR) Time-to-Digital Converter (TDC) of an ADPLL and a method for clock synchronization in an ADPLL are disclosed. In one embodiment, a clock synchronization unit of an ADPLL includes a two-flop synchronizer, a phase frequency detector (PFD) connected to the two-flop synchronizer, and a synchronization control circuit configured to control the two-flop synchronizer and the PFD to perform clock synchronization between a reference clock input signal and a divided clock input signal and to control the two-flop synchronizer and the PFD to replace a performance of the clock synchronization between the reference clock input signal and the divided clock input signal with a PFD operation. Other embodiments are also described.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: March 3, 2020
    Assignee: NXP B.V.
    Inventors: Nenad Pavlovic, Vladislav Dyachenko
  • Publication number: 20190383403
    Abstract: Flow control valves may be positioned downstream of water meters to increase pressure and compress entrained water vapour passing through the meters. However, turbulence within such valves can cause the valve's head to move radially, bending a shaft within the valve which may break. Accordingly, there is provided a flow control valve comprising: a housing having a flow passage; a valve seat defined within the flow passage; a valve head moveable to a closed position to engage the valve seat and seal the flow passage; a shaft secured to the valve head; a support slidingly mounting the shaft within the housing; a spring biasing the valve head to the closed position and configured to maintain the valve head in the closed position until a predetermined pressure is applied; and a guide assembly extending along at least a portion of the flow passage to constrain radial movement of the valve head.
    Type: Application
    Filed: June 6, 2019
    Publication date: December 19, 2019
    Inventors: RICHARD WACHTER, NENAD PAVLOVIC
  • Patent number: 10191453
    Abstract: A time to digital converter may include a synchronization block configured to output a voltage pulse with duration based on a time difference between a reference oscillating signal and an input oscillating signal; a charge pump arranged to receive the voltage pulse and to convert the voltage pulse into a current pulse; an integrator comprising an integrator capacitor, the integrator being configured to receive the current pulse and integrate the current pulse as a charge on the integrator capacitor, resulting in an integrator output voltage; and a successive approximation register configured to determine the integrator output voltage with respect to a reference voltage by adjusting the charge on the integrator capacitor so as to reduce the integrator output voltage to within a least significant bit (D0) of a reference voltage by successive approximation, and configured to output the determined integrator output voltage as a digital signal.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: January 29, 2019
    Assignee: NXP B.V.
    Inventors: Nenad Pavlovic, Vladislav Dyachenko, Tarik Saric
  • Publication number: 20180191364
    Abstract: A digitally controlled oscillator comprising a filtering digital to analogue converter, DAC, component and a voltage controlled oscillator, VCO, component comprising at least one control terminal arranged to receive a control voltage output by the DAC component; wherein the DAC component comprises a voltage generation component arranged to generate the control voltage and at least one configurable capacitive load component to which the control voltage is applied such that a filtering bandwidth of the DAC component is configurable by way of the at least one configurable capacitive load component.
    Type: Application
    Filed: December 21, 2017
    Publication date: July 5, 2018
    Inventor: Nenad Pavlovic
  • Patent number: 9611553
    Abstract: A hydrogen generator for producing hydrogen and oxygen gases comprising a housing having an electrolyte reservoir and an electrolysis cell, an electrical power source; a plurality of axially spaced-apart alternating positive and negative electrode plates mounted concentrically and separated from each other by a peripheral sealing ring in the electrolysis chamber; a pair of opposite tabs formed on the perimeter of the plates with openings for receiving an electrode support rod therein, positive electrode plates connected to a positive electrode support rod and negative electrode plates connected to a negative electrode support rod for electrically connecting the positive and the negative electrode plates to the power source, and fluid conduits for conveying liquid electrolyte from the reservoir to the electrolysis cell and for conveying hydrogen and oxygen gases from the electrolysis chamber; the electrode plates comprise a titanium plate having a 1-3 micron platinum coating, said plates preferably having a ci
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: April 4, 2017
    Inventors: Dejan Pavlovic, Nenad Pavlovic
  • Patent number: 9584177
    Abstract: A phase locked loop is disclosed having a frequency controlled oscillator, a feedback path, a time to digital converter and a memory. The frequency controlled oscillator comprises a first control input for varying the frequency of the output of the frequency controlled oscillator so as to track a reference frequency and a second control input for modulating the frequency of the output signal so as to produce a chirp. The feedback path is configured to provide an input signal to the time to digital converter, and comprises modulation cancelling module operable to remove the frequency modulation resulting from the second control input from the output signal. The memory stores second control input values that each correspond with a desired chirp frequency and which compensate for non-linearity in the response of the frequency controlled oscillator to the second control input.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: February 28, 2017
    Assignee: NXP B.V.
    Inventors: Nenad Pavlovic, Vladislav Dyachenko, Tarik Saric
  • Patent number: 9496889
    Abstract: A sigma delta receiver achieves increased stability and noise reduction. The sigma delta receiver includes a first integrator stage, an isolation stage, a second integrator stage, and a quantization stage. The first integrator stage receives an analog radio frequency (RF) signal from an antenna and generates an analog baseband signal based on the analog RF signal. The isolation stage is coupled to an output of the first integrator stage. The isolation stage receives the analog baseband signal from the first integrator stage and amplifies the analog baseband signal. The second integrator stage is coupled to an output of the isolation stage to receive the analog baseband signal. The second integrator stage further amplifies the analog baseband signal. The quantization stage converts the analog baseband signal to a digital signal, and outputs the digital signal.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: November 15, 2016
    Assignee: NXP B.V.
    Inventor: Nenad Pavlovic
  • Publication number: 20160238998
    Abstract: A time to digital converter (10) is disclosed.
    Type: Application
    Filed: February 11, 2016
    Publication date: August 18, 2016
    Inventors: Nenad Pavlovic, Vladislav Dyachenko, Tarik Saric
  • Publication number: 20160241301
    Abstract: A phase locked loop is disclosed having a frequency controlled oscillator (42), a feedback path, a time to digital converter (10) and a memory. The frequency controlled oscillator (42) comprises a first control input (135, 136) for varying the frequency of the output (106) of the frequency controlled oscillator (42) so as to track a reference frequency (101) and a second control input (139) for modulating the frequency of the output signal (106) so as to produce a chirp. The feedback path is configured to provide an input signal (107) to the time to digital converter (10), and comprises modulation cancelling module (14) operable to remove the frequency modulation resulting from the second control input (139) from the output signal (106). The memory stores second control input values that each correspond with a desired chirp frequency and which compensate for non-linearity in the response of the frequency controlled oscillator to the second control input (139).
    Type: Application
    Filed: February 11, 2016
    Publication date: August 18, 2016
    Inventors: NENAD PAVLOVIC, Vladislav DYACHENKO, Tarik SARIC
  • Patent number: 9413407
    Abstract: The invention relates to frequency conversion systems, in particular for use as up-converters or down-converters in radiofrequency (RF) receivers or transmitters, exemplary embodiments including a radiofrequency receiver including an RF signal input; a mixing module including a first plurality of IF amplifiers each connected to the RF signal input via a switch; a multi-phase local oscillator signal generator configured to provide a switching signal to each switch; and a summing module configured to receive output signals from each of the IF amplifiers and to provide a second plurality of output IF signals from a weighted sum of the IF amplifier output signals, wherein the second plurality is different to the first plurality.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: August 9, 2016
    Assignee: NXP B.V.
    Inventors: Jan van Sinderen, Johannes Hubertus Antonius Brekelmans, Frank Harald Erich Ho Chung Leong, Nenad Pavlovic
  • Publication number: 20160105196
    Abstract: A sigma delta receiver achieves increased stability and noise reduction. The sigma delta receiver includes a first integrator stage, an isolation stage, a second integrator stage, and a quantization stage. The first integrator stage receives an analog radio frequency (RF) signal from an antenna and generates an analog baseband signal based on the analog RF signal. The isolation stage is coupled to an output of the first integrator stage. The isolation stage receives the analog baseband signal from the first integrator stage and amplifies the analog baseband signal. The second integrator stage is coupled to an output of the isolation stage to receive the analog baseband signal. The second integrator stage further amplifies the analog baseband signal. The quantization stage converts the analog baseband signal to a digital signal, and outputs the digital signal.
    Type: Application
    Filed: October 13, 2014
    Publication date: April 14, 2016
    Applicant: NXP B.V.
    Inventor: Nenad Pavlovic
  • Patent number: 8961010
    Abstract: An x-ray system having a C-arm 1 and an associated method are provided. The x-ray system includes at least one adjustment unit for at least one component of the x-ray system that is actively connected to the C-arm. The at least one adjustment unit compensates for a spatial change in position of the component caused by deformation and/or oscillation of the C-arm.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: February 24, 2015
    Assignee: Siemens Aktiengesellschaft
    Inventors: Michael Meyer, Nenad Pavlovic
  • Patent number: 8922288
    Abstract: An oscillator circuit comprising first and second resonator terminals for connecting to respective terminals of a resonator. The oscillator circuit also comprises a first inverting amplifier connected between the first and second resonator terminals in a first mode of operation; and a back to back pair of second inverting amplifiers connected between the first and second resonator terminals in a second mode of operation. There is also provided a controller configured to compare an operational parameter of the oscillator circuit to a switchover threshold, and switch the oscillator circuit from the first mode of operation to the second mode of operation when the operational parameter exceeds the switchover threshold.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: December 30, 2014
    Assignee: NXP, B.V.
    Inventors: Johannes Hubertus Antonius Brekelmans, Reinier Hoogendoorn, Nenad Pavlovic
  • Patent number: 8872596
    Abstract: The present invention relates to a polar signal generator and method of deriving phase and amplitude components from in-phase (I) and quadrature-phase (Q) components of an input signal, wherein the I and Q components are generated at a first sampling frequency based on the input signal, and are then up-sampled in accordance with a predetermined first interpolation factor (N), to generate up-sampled I and Q components at a second sampling frequency higher than the first sampling frequency. The up-sampled I and Q components are converted into the phase and amplitude components, wherein the converting step is operated at the second sampling frequency. Moreover, the phase and amplitude components can be further up-sampled, optionally by different sampling frequencies, to a third and a fourth sampling frequency. Thereby, I-Q generation and cartesian-to-polar transformation can be performed at lower frequencies, which reduces power consumption.
    Type: Grant
    Filed: June 6, 2007
    Date of Patent: October 28, 2014
    Assignee: NXP, B.V.
    Inventors: Manel Collados Asensio, Nenad Pavlovic, Vojkan Vidojkovic, Paulus T. M. Van Zeijl
  • Patent number: 8638174
    Abstract: The invention relates to a digital signal generator for providing one or more phases of a local oscillator signal for use in digital to analogue converters and harmonic rejection mixers. Embodiments disclosed include a local oscillator signal generator (200) for a mixer of a radiofrequency receiver, the signal generator (200) comprising a bit sequence generator (201) having a plurality of parallel output lines (203), a digital signal generator (202) having a serial output line (204) and a plurality of input lines connected to respective output lines (203) of the bit sequence generator (201) and a clock signal input line (205), wherein the digital signal generator (202) is configured to provide an output bit sequence on the serial output line (204) at a rate given by a clock signal provided on the clock signal input line (205) and a sequence given by a sequence of bits from the bit sequence generator (201) on the plurality of input lines (203).
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: January 28, 2014
    Assignee: Integrated Device Technology inc.
    Inventors: Nenad Pavlovic, Johannes Hubertus Antonius Brekelmans, Jan van Sinderen
  • Patent number: 8571134
    Abstract: The present application relates to at least one digitally controlled oscillator and a data modulation device. More particularly, the digital polar transmitter comprises at least one digitally controlled oscillator configured to generate at least one frequency. The digital polar transmitter comprises a data modulation device, wherein the data modulation device comprises at least one data input terminal, at least one output terminal, and at least one frequency input terminal, wherein the output terminal is connected to the digitally controlled oscillator. The digital polar transmitter comprises a phase measuring device configured to measure phase information from the output signal of the data modulation device for every frequency sample.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: October 29, 2013
    Assignee: NXP, B.V.
    Inventors: Nenad Pavlovic, Manel Collados, Xin He, Jan Van Sinderen
  • Publication number: 20130202093
    Abstract: An x-ray system having a C-arm 1 and an associated method are provided. The x-ray system includes at least one adjustment unit for at least one component of the x-ray system that is actively connected to the C-arm. The at least one adjustment unit compensates for a spatial change in position of the component caused by deformation and/or oscillation of the C-arm.
    Type: Application
    Filed: February 7, 2013
    Publication date: August 8, 2013
    Inventors: Michael Meyer, Nenad Pavlovic
  • Patent number: 8472620
    Abstract: A portable electronic device for exchanging encrypted data with other electronic devices includes a processor, a memory operatively coupled to the processor, and a prime number generation circuit operatively coupled to the processor and memory. The prime number generation circuit includes logic that generates at least two prime numbers based on unique data stored in the electronic device, wherein said at least two prime numbers are always the same at least two prime numbers. The generated prime numbers then can be used to generate RSA public and private keys within the electronic device.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: June 25, 2013
    Assignees: Sony Corporation, Sony Mobile Communications AB
    Inventor: Nenad Pavlovic
  • Publication number: 20130105307
    Abstract: A hydrogen generator for producing hydrogen and oxygen gases comprising a housing having an electrolyte reservoir and an electrolysis cell, an electrical power source; a plurality of axially spaced-apart alternating positive and negative electrode plates mounted concentrically and separated from each other by a peripheral sealing ring in the electrolysis chamber; a pair of opposite tabs formed on the perimeter of the plates with openings for receiving an electrode support rod therein, positive electrode plates connected to a positive electrode support rod and negative electrode plates connected to a negative electrode support rod for electrically connecting the positive and the negative electrode plates to the power source, and fluid conduits for conveying liquid electrolyte from the reservoir to the electrolysis cell and for conveying hydrogen and oxygen gases from the electrolysis chamber; the electrode plates comprise a titanium plate having a 1-3 micron platinum coating, said plates preferably having a ci
    Type: Application
    Filed: October 31, 2012
    Publication date: May 2, 2013
    Inventors: Dejan Pavlovic, Nenad Pavlovic
  • Patent number: 8362932
    Abstract: Calibration data for calibrating time to digital conversion is obtained by switching a feed circuit of a time to digital converter between a normal operating mode or a calibration mode. A delay circuit with a delay circuit input and a plurality of taps outputs. A sampling register samples data from the data inputs. The feed circuit provides for selection of transitions of the oscillator signal that control timing of a first active transition at the clock circuit after a transition at the delay circuit input. A control circuit switches the feed circuit between normal operating mode and calibration mode, and controls the feed circuit successively to select a plurality of different transitions to control timing of the first active transition in the calibration mode. The control circuit reads out resulting data from the sampling register for each selection and determines calibration data for the oscillator signal from said data.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: January 29, 2013
    Assignee: ST-Ericsson SA
    Inventors: Nenad Pavlovic, Manel Collados Asensio, Xin He, Jan Van Sinderen