Patents by Inventor NEVILLE L. DIAS

NEVILLE L. DIAS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10964690
    Abstract: Techniques are disclosed for forming semiconductor structures including resistors between gates on self-aligned gate edge architecture. A semiconductor structure includes a first semiconductor fin extending in a first direction, and a second semiconductor fin adjacent to the first semiconductor fin, extending in the first direction. A first gate structure is disposed proximal to a first end of the first semiconductor fin and over the first semiconductor fin in a second direction, orthogonal to the first direction, and a second gate structure is disposed proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction. A first structure comprising isolation material is centered between the first and second semiconductor fins. A second structure comprising resistive material is disposed in the first structure, the second structure extending at least between the first gate structure and the second gate structure.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Roman W. Olac-Vaw, Walid M. Hafez, Chia-Hong Jan, Hsu-Yu Chang, Neville L. Dias, Rahul Ramaswamy, Nidhi Nidhi, Chen-Guan Lee
  • Patent number: 10930729
    Abstract: Fin-based thin film resistors, and methods of fabricating fin-based thin film resistors, are described. In an example, an integrated circuit structure includes a fin protruding through a trench isolation region above a substrate. The fin includes a semiconductor material and has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. An isolation layer is conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A resistor layer is conformal with the isolation layer conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A first anode cathode electrode is electrically connected to the resistor layer. A second anode or cathode electrode is electrically connected to the resistor layer.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Chia-Hong Jan, Walid M. Hafez, Neville L. Dias, Rahul Ramaswamy, Hsu-Yu Chang, Roman W. Olac-Vaw, Chen-Guan Lee
  • Patent number: 10854607
    Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Chia-Hong Jan, Walid M Hafez, Jeng-Ya David Yeh, Hsu-Yu Chang, Neville L Dias, Chanaka D Munasinghe
  • Patent number: 10854757
    Abstract: A transistor including a channel disposed between a source and a drain, a gate electrode disposed on the channel and surrounding the channel, wherein the source and the drain are formed in a body on a substrate and the channel is separated from the body. A method of forming an integrated circuit device including forming a trench in a dielectric layer on a substrate, the trench including dimensions for a transistor body including a width; forming a channel material in the trench; recessing the dielectric layer to expose a first portion of the channel material; increasing a width dimension of the exposed channel material; recessing the dielectric layer to expose a second portion of the channel material; removing the second portion of the channel material; and forming a gate stack on the first portion of the channel material, the gate stack including a gate dielectric and a gate electrode.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Rahul Ramaswamy, Hsu-Yu Chang, Chia-Hong Jan, Walid M. Hafez, Neville L. Dias, Roman W. Olac-Vaw, Chen-Guan Lee
  • Patent number: 10756210
    Abstract: A transistor device including a transistor including a body disposed on a substrate, a gate stack contacting at least two adjacent sides of the body and a source and a drain on opposing sides of the gate stack and a channel defined in the body between the source and the drain, wherein a conductivity of the channel is similar to a conductivity of the source and the drain. An input/output (IO) circuit including a driver circuit coupled to the logic circuit, the driver circuit including at least one transistor device is described. A method including forming a channel of a transistor device on a substrate including an electrical conductivity; forming a source and a drain on opposite sides of the channel, wherein the source and the drain include the same electrical conductivity as the channel; and forming a gate stack on the channel.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Chia-Hong Jan, Walid M. Hafez, Hsu-Yu Chang, Neville L. Dias, Rahul Ramaswamy, Roman W. Olac-Vaw, Chen-Guan Lee
  • Publication number: 20200251471
    Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.
    Type: Application
    Filed: April 20, 2020
    Publication date: August 6, 2020
    Applicant: Intel Corporation
    Inventors: Chia-Hong Jan, Walid M. Hafez, Jeng-Ya David Yeh, Hsu-Yu Chang, Neville L. Dias, Chanaka D. Munasinghe
  • Patent number: 10643999
    Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Chia-Hong Jan, Walid M Hafez, Jeng-Ya David Yeh, Hsu-Yu Chang, Neville L Dias, Chanaka D Munasinghe
  • Publication number: 20200066907
    Abstract: A transistor device including a transistor including a body disposed on a substrate, a gate stack contacting at least two adjacent sides of the body and a source and a drain on opposing sides of the gate stack and a channel defined in the body between the source and the drain, wherein a conductivity of the channel is similar to a conductivity of the source and the drain. An input/output (IO) circuit including a driver circuit coupled to the logic circuit, the driver circuit including at least one transistor device is described. A method including forming a channel of a transistor device on a substrate including an electrical conductivity; forming a source and a drain on opposite sides of the channel, wherein the source and the drain include the same electrical conductivity as the channel; and forming a gate stack on the channel.
    Type: Application
    Filed: September 30, 2016
    Publication date: February 27, 2020
    Inventors: Chia-Hong JAN, Walid M. HAFEZ, Hsu-Yu CHANG, Neville L. DIAS, Rahul RAMASWAMY, Roman W. OLAC-VAW, Chen-Guan LEE
  • Publication number: 20200043914
    Abstract: Techniques are disclosed for forming semiconductor structures including resistors between gates on self-aligned gate edge architecture. A semiconductor structure includes a first semiconductor fin extending in a first direction, and a second semiconductor fin adjacent to the first semiconductor fin, extending in the first direction. A first gate structure is disposed proximal to a first end of the first semiconductor fin and over the first semiconductor fin in a second direction, orthogonal to the first direction, and a second gate structure is disposed proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction. A first structure comprising isolation material is centered between the first and second semiconductor fins. A second structure comprising resistive material is disposed in the first structure, the second structure extending at least between the first gate structure and the second gate structure.
    Type: Application
    Filed: March 31, 2017
    Publication date: February 6, 2020
    Applicant: INTEL CORPORATION
    Inventors: ROMAN W. OLAC-VAW, WALID M. HAFEZ, CHIA-HONG JAN, HSU-YU CHANG, NEVILLE L. DIAS, RAHUL RAMASWAMY, NIDHI NIDHI, CHEN-GUAN LEE
  • Publication number: 20190304840
    Abstract: An apparatus comprising at least one transistor in a first area of a substrate and at least one transistor in a second area, a work function material on a channel region of each of the at least one transistor, wherein an amount of work function material in the first area is different than an amount of work function material in the second area. A method comprising depositing a work function material and a masking material on at least one transistor body in a first area and at least one in a second area; removing less than an entire portion of the masking material so that the portion of the work function material that is exposed in the first area is different than that exposed in the second area; removing the exposed work function material; and forming a gate electrode on each of the at least one transistor bodies.
    Type: Application
    Filed: September 30, 2016
    Publication date: October 3, 2019
    Inventors: Chen-Guan LEE, Everett S. CASSIDY-COMFORT, Joodong PARK, Walid M. HAFEZ, Chia-Hong JAN, Rahul RAMASWAMY, Neville L. DIAS, Hsu-Yu CHANG
  • Publication number: 20190287973
    Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.
    Type: Application
    Filed: June 3, 2019
    Publication date: September 19, 2019
    Applicant: Intel Corporation
    Inventors: Chia-Hong Jan, Walid M. Hafez, Jeng-Ya David Yeh, Hsu-Yu Chang, Neville L. Dias, Chanaka D. Munasinghe
  • Publication number: 20190245098
    Abstract: A transistor including a channel disposed between a source and a drain, a gate electrode disposed on the channel and surrounding the channel, wherein the source and the drain are formed in a body on a substrate and the channel is separated from the body. A method of forming an integrated circuit device including forming a trench in a dielectric layer on a substrate, the trench including dimensions for a transistor body including a width; forming a channel material in the trench; recessing the dielectric layer to expose a first portion of the channel material; increasing a width dimension of the exposed channel material; recessing the dielectric layer to expose a second portion of the channel material; removing the second portion of the channel material; and forming a gate stack on the first portion of the channel material, the gate stack including a gate dielectric and a gate electrode.
    Type: Application
    Filed: December 13, 2016
    Publication date: August 8, 2019
    Inventors: Rahul RAMASWAMY, Hsu-Yu CHANG, Chia-Hong JAN, Walid M. HAFEZ, Neville L. DIAS, Roman W. OLAC-VAW, Chen-Guan LEE
  • Publication number: 20190237564
    Abstract: A transistor including a source and a drain each formed in a substrate; a channel disposed in the substrate between the source and drain, wherein the channel includes opposing sidewalls with a distance between the opposing sidewalls defining a width dimension of the channel and wherein the opposing sidewalls extend a distance below a surface of the substrate; and a gate electrode on the channel. A method of forming a transistor including forming a source and a drain in an area of a substrate; forming a source contact on the source and a drain contact on the drain; after forming the source contact and the drain contact, forming a channel in the substrate in an area between the source and drain, the channel including a body having opposing sidewalls separated by a length dimension; and forming a gate contact on the channel.
    Type: Application
    Filed: December 12, 2016
    Publication date: August 1, 2019
    Inventors: Chia-Hong JAN, Walid M. HAFEZ, Neville L. DIAS, Rahul RAMASWAMY, Hsu-Yu CHANG, Roman W. OLAC-VAW, Chen-Guan LEE
  • Publication number: 20190206980
    Abstract: Fin-based thin film resistors, and methods of fabricating fin-based thin film resistors, are described. In an example, an integrated circuit structure includes a fin protruding through a trench isolation region above a substrate. The fin includes a semiconductor material and has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. An isolation layer is conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A resistor layer is conformal with the isolation layer conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A first anode cathode electrode is electrically connected to the resistor layer. A second anode or cathode electrode is electrically connected to the resistor layer.
    Type: Application
    Filed: October 21, 2016
    Publication date: July 4, 2019
    Inventors: Chia-Hong JAN, Walid M. HAFEZ, Neville L. DIAS, Rahul RAMASWAMY, Hsu-Yu CHANG, Roman W. OLAC-VAW, Chen-Guan LEE
  • Patent number: 10340273
    Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Chia-Hong Jan, Walid M Hafez, Jeng-Ya David Yeh, Hsu-Yu Chang, Neville L Dias, Chanaka D Munasinghe
  • Publication number: 20190097057
    Abstract: An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein.
    Type: Application
    Filed: November 29, 2018
    Publication date: March 28, 2019
    Inventors: Neville L. Dias, Chia-Hong Jan, Walid M. Hafez, Roman W. Olac-Vaw, Hsu-Yu Chang, Ting Chang, Rahul Ramaswamy, Pei-Chi Liu
  • Patent number: 10164115
    Abstract: An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Neville L. Dias, Chia-Hong Jan, Walid M. Hafez, Roman W. Olac-Vaw, Hsu-Yu Chang, Ting Chang, Rahul Ramaswamy, Pei-Chi Liu
  • Publication number: 20180323260
    Abstract: Embodiments of the present invention are directed to dual threshold voltage (VT) channel devices and their methods of fabrication. In an example, a semiconductor device includes a gate stack disposed on a substrate, the substrate having a first lattice constant. A source region and a drain region are formed on opposite sides of the gate electrode. A channel region is disposed beneath the gate stack and between the source region and the drain region. The source region is disposed in a first recess having a first depth and the drain region disposed in a second recess having a second depth. The first recess is deeper than the second recess. A semiconductor material having a second lattice constant different than the first lattice constant is disposed in the first recess and the second recess.
    Type: Application
    Filed: December 23, 2015
    Publication date: November 8, 2018
    Inventors: Hsu-Yu CHANG, Neville L. DIAS, Walid M. HAFEZ, Chia-Hong JAN, Roman W. OLAC-VAW, Chen-Guan LEE
  • Patent number: 9947585
    Abstract: An embodiment includes an apparatus comprising: a non-planar transistor comprising a fin, the fin including a source region having a source region width and a source region height, a channel region having a channel region width and a channel region height, a drain region having a drain width and a drain height, and a gate dielectric formed on a sidewall of the channel region; wherein the apparatus includes at least one of (a) the channel region width being wider than the source region width, and (b) the gate dielectric including a first gate dielectric thickness at a first location and a second gate dielectric thickness at a second location, the first and second locations located at an equivalent height on the sidewall and the first and second gate dielectrics thicknesses being unequal to one another. Other embodiments are described herein.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: April 17, 2018
    Assignee: Intel Corporation
    Inventors: Nidhi Nidhi, Chia-Hong Jan, Roman W. Olac-Vaw, Hsu-Yu Chang, Neville L. Dias, Walid M. Hafez, Rahul Ramaswamy
  • Publication number: 20170125419
    Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.
    Type: Application
    Filed: January 18, 2017
    Publication date: May 4, 2017
    Inventors: Chia-Hong Jan, Walid M. Hafez, Jeng-Ya David Yeh, Hsu-Yu Chang, Neville L. Dias, Chanaka D. Munasinghe