Patents by Inventor Nhu-Ha Yup

Nhu-Ha Yup has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9866370
    Abstract: Architecture for embedding a cryptographic engine in a processor is disclosed. An ASIC processor is embedded with a programmable processing core, such as an FPGA, with the key register and I/O registers remaining in fixed logic.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: January 9, 2018
    Assignee: ITT MANUFACTURING ENTERPRISES, LLC
    Inventors: Bryan Doi, Kevin Osugi, Nhu-Ha Yup, Richard Takahashi
  • Patent number: 9209967
    Abstract: An authenticated encryption method includes receiving, by an Advanced Encryption Standard (AES) engine, a cipher key and computing a hash key using the received cipher key. The computed hash key is stored in a storage memory. The AES engine then receives a packet of data and encrypts the packet of data using the received cipher key. The hash key from the storage memory is sent to a GHASH engine which is used to authenticate the packet of data. Encrypting the packet of data is performed after the hash key is stored in the storage memory. Input flow of the packet of data is enabled after the hash key is stored in the storage memory.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: December 8, 2015
    Assignee: Exelis, Inc.
    Inventor: Nhu-Ha Yup
  • Patent number: 8850225
    Abstract: A combination firmware and hardware cryptographic core architecture is provided for encrypting, decrypting and authenticating data. The core provides flexibility to change and add new cryptographic protocols, while providing increased performance by loading new firmware into a microcontroller that programs behavior of various components in the core. The core combines a microcontroller programmable by firmware, and flexible aligner, insertion and removal controllers programmed by the microcontroller that process, manage and manipulate an incoming data stream as it moves through the core. The firmware may be reprogrammed upon an enhancement or change to a protocol while still realizing performance benefits of the hardware. Reprogramming the microcontroller allows it to change the way the aligner, insertion and removal controllers manipulate the data stream as it enters various components.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: September 30, 2014
    Assignee: Exelis Inc.
    Inventors: Lee Noehring, Kevin Osugi, Darren Parker, Nhu-Ha Yup
  • Patent number: 8707051
    Abstract: A firmware cipher component is provided which can be configured and programmed to efficiently implement a broad range of cryptographic ciphers while accelerating their processing. This firmware cipher component allows an ASIC to support multiple cipher algorithms while accelerating the operations beyond speeds conventionally achieved by software or firmware only solutions. This system combines cryptographic specific custom instructions with hardware based data manipulation accelerators. The cryptographic specific custom instructions and hardware accelerators may support both block and stream ciphers. Thus, the system may be reconfigured, allowing the cipher algorithm to change without halting the system. Further, embedding the Firmware Programmable Cipher within an ASIC may allow future capabilities to be supported in secure applications.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: April 22, 2014
    Assignee: Exelis, Inc.
    Inventors: Kevin Joel Osugi, Nhu-Ha Yup, Michael D. Collins, Lee Paul Noehring
  • Publication number: 20120311348
    Abstract: A firmware cipher component is provided which can be configured and programmed to efficiently implement a broad range of cryptographic ciphers while accelerating their processing. This firmware cipher component allows an ASIC to support multiple cipher algorithms while accelerating the operations beyond speeds conventionally achieved by software or firmware only solutions. This system combines cryptographic specific custom instructions with hardware based data manipulation accelerators. The cryptographic specific custom instructions and hardware accelerators may support both block and stream ciphers. Thus, the system may be reconfigured, allowing the cipher algorithm to change without halting the system. Further, embedding the Firmware Programmable Cipher within an ASIC may allow future capabilities to be supported in secure applications.
    Type: Application
    Filed: June 4, 2012
    Publication date: December 6, 2012
    Inventors: Kevin Joel Osugi, Nhu-Ha Yup, Michael D. Collins, Lee Paul Noehring
  • Publication number: 20110258457
    Abstract: A combination firmware and hardware cryptographic core architecture is provided for encrypting, decrypting and authenticating data. The core provides flexibility to change and add new cryptographic protocols, while providing increased performance by loading new firmware into a microcontroller that programs behavior of various components in the core. The core combines a microcontroller programmable by firmware, and flexible aligner, insertion and removal controllers programmed by the microcontroller that process, manage and manipulate an incoming data stream as it moves through the core. The firmware may be reprogrammed upon an enhancement or change to a protocol while still realizing performance benefits of the hardware. Reprogramming the microcontroller allows it to change the way the aligner, insertion and removal controllers manipulate the data stream as it enters various components.
    Type: Application
    Filed: April 16, 2010
    Publication date: October 20, 2011
    Inventors: Lee Noehring, Kevin Osugi, Darren Parker, Nhu-Ha Yup
  • Publication number: 20100027783
    Abstract: An authenticated encryption method includes receiving, by an Advanced Encryption Standard (AES) engine, a cipher key and computing a hash key using the received cipher key. The computed hash key is stored in a storage memory. The AES engine then receives a packet of data and encrypts the packet of data using the received cipher key. The hash key from the storage memory is sent to a GHASH engine which is used to authenticate the packet of data. Encrypting the packet of data is performed after the hash key is stored in the storage memory. Input flow of the packet of data is enabled after the hash key is stored in the storage memory.
    Type: Application
    Filed: March 12, 2007
    Publication date: February 4, 2010
    Inventor: Nhu-Ha Yup
  • Publication number: 20090147945
    Abstract: Architecture for embedding a cryptographic engine in a processor is disclosed. An ASIC processor is embedded with a programmable processing core, such as an FPGA, with the key register and I/O registers remaining in fixed logic.
    Type: Application
    Filed: December 5, 2007
    Publication date: June 11, 2009
    Applicant: ITT MANUFACTURING ENTERPRISES, INC.
    Inventors: Bryan Doi, Kevin Osugi, Nhu-Ha Yup, Richard Takahashi
  • Patent number: 6937727
    Abstract: A circuit includes a single circuit portion for implementing the Advanced Encryption Standard (AES) block cipher algorithm in a system having a plurality of channels. The circuit portion includes a circuit for individually generating, on the fly, the round keys used during each round of the AES block cipher algorithm. The circuit portion also includes shared logic circuits that implement the transformations used to encrypt and decrypt data blocks according to the AES block cipher. The single circuit portion encrypts or decrypts data blocks from each of the plurality of system channels in turn, in round-robin fashion. The circuit portion also includes a circuit for determining S-box values for the AES block cipher algorithm. The circuit additionally implements an efficient method for generating round keys on the fly for the AES block cipher decryption process.
    Type: Grant
    Filed: June 8, 2001
    Date of Patent: August 30, 2005
    Assignee: Corrent Corporation
    Inventors: Nhu-Ha Yup, Satish N. Anand
  • Publication number: 20020191784
    Abstract: A circuit includes a single circuit portion for implementing the Advanced Encryption Standard (AES) block cipher algorithm in a system having a plurality of channels. The circuit portion includes a circuit for individually generating, on the fly, the round keys used during each round of the AES block cipher algorithm. The circuit portion also includes shared logic circuits that implement the transformations used to encrypt and decrypt data blocks according to the AES block cipher. The single circuit portion encrypts or decrypts data blocks from each of the plurality of system channels in turn, in round-robin fashion. The circuit portion also includes a circuit for determining S-box values for the AES block cipher algorithm. The circuit additionally implements an efficient method for generating round keys on the fly for the AES block cipher decryption process.
    Type: Application
    Filed: June 8, 2001
    Publication date: December 19, 2002
    Inventors: Nhu-Ha Yup, Satish N. Anand