Abstract: A resampler, method of resampling a signal and a bit pump and transceiver employing the same. In one embodiment, the resampler includes an interpolation stage, coupled to an input of the resampler, that receives a one-bit input signal representing at least a portion of a receive signal propagating along a receive path of the bit pump and generates a plurality of intermediate samples from at least two input samples associated with the one-bit input signal. The resampler also includes a selection stage, coupled to the interpolation stage, that receives the plurality of intermediate samples via one delay line of single bits and select one thereof, thereby providing an output sample that corresponds to a phase of the oscillator.

Abstract: A resampler, method of resampling a signal and a bit pump and transceiver employing the same. In one embodiment, the resampler includes an interpolation stage, coupled to an input of the resampler, that receives a one-bit input signal representing at least a portion of a receive signal propagating along a receive path of the bit pump and generates a plurality of intermediate samples from at least two input samples associated with the one-bit input signal. The resampler also includes a selection stage, coupled to the interpolation stage, that selects one of the plurality of intermediate samples thereby providing an output sample that corresponds to a phase of an oscillator associated with the bit pump.

Abstract: A filter circuit, method of configuring the filter circuit, and a bit pump and transceiver employing the circuit and method. In one embodiment, the filter circuit includes a noise prediction equalizer that generates a noise prediction equalizer coefficient during activation of the bit pump to reduce an intersymbol interference associated with a receive signal propagating along a receive path of the bit pump. The filter circuit also includes a decision feedback equalizer that generates a decision feedback equalizer coefficient during the activation of the bit pump to reduce the intersymbol interference associated with the receive signal. The noise prediction equalizer is concatenated with the decision feedback equalizer during showtime of the bit pump to form a precoder associated with a transmit path of the bit pump.

Abstract: A low precision Finite Impulse Response filter (FIR) is provided for filtering in a digital interpolation operation. The interpolation operation is comprised of two steps, a sampling rate conversion operation for interspersing zeroes between samples in an input sequence and a filtering step of filtering out images that result from this operation. The filtering operation utilizes a FIR filter that utilizes a low precision set of filter coefficients that are selected to tune the frequency response such that the low end frequency response including the pass band, the transition band, and the portion of the stop band immediately after the transition band provides a response equivalent to that commensurate with substantially higher precision FIR filter coefficients. A second, low pass filter section is provided for filtering the high frequency image energy at the output of the FIR filter to provide an overall filter response commensurate to that utilizing substantially higher precision FIR coefficients.

Abstract: A calibration method and apparatus to calibrate for non-linearities in a multi-level delta-sigma modulator (12) includes a calibration multiplexer (10) on the input for selecting in a calibration mode a zero voltage for input to the delta-sigma modulator (12). The delta-sigma modulator (12) has three levels, +1, 0, -1, the +1 level input to a processor (32) and the -1 level input to a processor (34). The processor (34) has the output thereof input to an compensation circuit (14) that offsets the value generated by the -1 processor (34) by a coefficient .delta.. The output of the compensation circuit (14) is then input to the minus input of a summation junction (36), which also receives the output of the processor (32), the output of summation junction (36) providing the digital output. The processors (32) and (34) are realized with a separate accumulator that switches between an associated filter coefficient and ground, the filter coefficient stored in a ROM (35). The .delta.

Abstract: A transient-error free interpolating decimator utilizes only two comb filters. The decimator has an integrator circuit, which receives a digitized signal at a first clock rate, and a differentiator circuit. The differentiator includes first and second comb filters for down converting the digital signal at the first clock rate to a second clock rate, and for providing sample points at first and second outputs; the differentiator circuit and the integrator circuit comprise a decimation filter. A delay circuit provides coarse sampling phase adjustments by delaying the second clock rate by a predetermined number of first-clock cycles. A counter generates the second clock rate and provides coarse sampling phase adjustments by adding or deleting cycles of the first clock to or form the second clock. A multiplexer circuit swaps the two outputs when necessary to prevent transient errors generated in the differentiators from being observed.

Abstract: A digital tone detector receives a modulated input signal selectively containing at least one tone signal component. Two demodulator circuits each demodulate the input signal wherein one demodulator circuit operates at the predetermined frequency of the tone and the other demodulator circuit operates at the second harmonic. When the input tone has a low spectral harmonic power, a ratio of the demodulated outputs of the two demodulators reliably detects the presence of the tone in the input signal.

Abstract: A noise shaping modulator for use in sigma delta modulation data conversion has two or more cascaded quantization loops. A first quantization loop is operated at a first sampling frequency and one or more higher order quantization loops are operated at a second sampling frequency. Due to speed limitations of analog circuitry in the first quantization loop, a significant improvement in signal to noise ratio may be achieved in a sigma delta modulation data converter by selecting the second sampling frequency higher than the first sampling frequency.

Abstract: An oversampling A/D converter for high resolution data conversion is provided. An analog input signal is quantized into a digital equivalent value with a finite quantization error associated therewith in a first circuit portion. An analog low pass filter is inserted between the first circuit portion and a second circuit portion similar in function and circuitry to the first circuit portion. The second circuit portion functions to remove the error of the first circuit portion from an output signal by providing a signal component, which when added with the output of the first circuit portion cancels the error of the first circuit portion. The low pass filter provides attenuation of quantization error provided by the second circuit portion which results in an output signal with a significantly attenuated error.

Abstract: An oversampled A/D converter which utilizes digital error correction is provided. In one form, the present invention is used with a sigma delta modulator having a plurality of rank ordered quantization loops, Each quantization loop contains an analog integrator circuit of predetermined gain which is subject to variation, thereby introducing errors. When the product of a reciprocal of the analog integrator gain and the gain of a digital gain stage of a subsequent quantization loop equals one, minimum noise exists in the data conversion. A digital gain control circuit is coupled to the digital gain stage for adjusting the gain of the digital gain stage during a calibration mode to provide minimum noise in the converter, thereby compensating for errors attributable to the analog integrator circuit.