Patents by Inventor Nicolas Loubet

Nicolas Loubet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10665497
    Abstract: The method of manufacturing a structure comprising one or several strained semiconducting zones capable of forming one or several transistor channel regions, the method including the following steps: a) providing a substrate coated with a masking layer wherein there are one or several first slits exposing one or several first oblong semiconducting portions made of a first semiconducting material and extending in a first direction, b) making a second semiconducting material grow with a mesh parameter different from the mesh parameter of the first semiconducting material, so as to form one or several first semiconducting blocks strained along the first direction, on said one or several first oblong semiconducting portions.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: May 26, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS Inc
    Inventors: Emmanuel Augendre, Nicolas Loubet, Sylvain Maitrejean, Pierre Morin
  • Publication number: 20200161299
    Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Inventors: Qing LIU, Prasanna KHARE, Nicolas LOUBET
  • Publication number: 20200144385
    Abstract: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, a trench contact formed on and in contact with the source/drain, and a source/drain contact formed on an in contact with the trench contact. A recess is formed in a portion of the source/drain contact using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the source/drain contact. A metallization layer is formed in contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.
    Type: Application
    Filed: January 3, 2020
    Publication date: May 7, 2020
    Applicant: International Business Machines Corporation
    Inventors: Julien Frougier, Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng
  • Patent number: 10636694
    Abstract: A semiconductor device is fabricated with a first layer of a first sacrificial material deposited over a surface of a substrate. A first set of layers of a second sacrificial material and a second set of layers of a channel material are deposited over the first layer. A liner is deposited in a first recess, which exposes a first connection end of a layer in the second set, where the first recess reaches into the substrate for at least a fraction of a total depth of the substrate. An insulator material is filled in the first recess and etched up to a stop depth, stopping the etching at a height above the surface of the substrate. The liner is removed from at least the first connection end of the layer in the second set. An electrical connection is formed with a source/drain structure using the first connection end.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: April 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robin Hsin Kuo Chao, Kangguo Cheng, Nicolas Loubet, Pietro Montanini, Ruilong Xie
  • Publication number: 20200126987
    Abstract: Devices and methods are provided for fabricating metallic interlayer via contacts within source/drain regions of field-effect transistor devices of a monolithic three-dimensional semiconductor integrated circuit device. For example, a semiconductor integrated circuit device includes a first device layer and a second device layer disposed on the first device layer. The first device layer includes a metallic interconnect structure formed in an insulating layer. The second device layer includes first and second field-effect transistor devices having respective first and second gate structures. A metallic interlayer via contact is disposed between the first and second gate structures in contact with the metallic interconnect structure of the first device layer, wherein a width of the metallic interlayer via contact is defined by a spacing between adjacent sidewalls of the first and second gate structures.
    Type: Application
    Filed: October 22, 2018
    Publication date: April 23, 2020
    Inventors: Joshua M. Rubin, Nicolas Loubet, Terence B. Hook
  • Publication number: 20200105869
    Abstract: A technique relates to a semiconductor device. A stack is formed over a bottom sacrificial layer, the bottom sacrificial layer being on a substrate. At least a portion of the bottom sacrificial layer is removed so as to create openings. Inner spacers are formed in the openings adjacent to the bottom sacrificial layer. The bottom sacrificial layer is removed so as to create a void. An isolation layer formed on the inner spacers so as to form an air gap, the isolation layer and the air gap being positioned between the stack and the substrate.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Nicolas LOUBET, Robin Hsin Kuo CHAO, Julien FROUGIER, Ruilong XIE
  • Publication number: 20200105868
    Abstract: A technique relates to a semiconductor device. A bottom sacrificial layer is formed on a substrate. A stack is formed over the bottom sacrificial layer and a dummy gate is formed over the stack. The bottom sacrificial layer is removed from under the stack so as to leave an opening. An isolation layer is formed in the opening, the isolation layer being positioned between the stack and the substrate.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Nicolas LOUBET, Robin Hsin Kuo CHAO, Julien FROUGIER, Ruilong XIE
  • Publication number: 20200098760
    Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Inventors: Pierre MORIN, Nicolas LOUBET
  • Publication number: 20200098859
    Abstract: A method for making first and second superimposed transistors, including: making, on a substrate, a stack of several semiconducting nanowires; etching a first nanowire so that a remaining portion of the first nanowire forms a channel of the first transistor; etching a second nanowire arranged between the substrate and the first nanowire, so that a remaining portion of the second nanowire forms a channel of the second transistor and has a greater length than that of the remaining portion of the first nanowire; making second source and drain regions in contact with ends of the remaining portion of the second nanowire; depositing a first dielectric encapsulation layer covering the second source and drain regions and forming vertical insulating portions; making first source and drain regions in contact with ends of the remaining portion of the first nanowire and insulated from the second source and drain regions by the vertical insulating portions.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 26, 2020
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, International Business Machines Corporation
    Inventors: Shay Reboh, Remi Coquand, Nicolas Loubet, Tenko Yamashita, Jingyun Zhang
  • Publication number: 20200083384
    Abstract: A method of fabricating a nanosheet semiconductor device includes depositing sacrificial material on a layer of silicon germanium (SiGe) above a substrate. A thickness of the sacrificial material is more than a thickness of the layer of SiGe. The method also includes forming nanosheet fins comprising alternating silicon (Si) nanosheets and silicon germanium (SiGe) layers on the sacrificial material, undercutting the SiGe layers to form divots, and forming a dummy gate structure above each of the nanosheet fins. A first liner is deposited to fill the divots and cover the nanosheet fins and the dummy gate structure. The sacrificial material and the first liner material are removed. The method also includes encapsulating the nanosheet fins and the dummy gate structure with a conformal liner, and performing an oxide fill to create a buried oxide (BOX) isolation between subsequently formed source and drain regions between the nanosheet fins and the substrate.
    Type: Application
    Filed: September 12, 2018
    Publication date: March 12, 2020
    Inventors: Julien Frougier, Kangguo Cheng, Nicolas Loubet, Ruilong Xie
  • Publication number: 20200083376
    Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 12, 2020
    Inventors: Pierre Morin, Nicolas Loubet
  • Patent number: 10586856
    Abstract: A semiconductor device is described. The semiconductor device includes a nanosheet stack including a sacrificial nanosheet oriented substantially parallelly to a substrate and a channel nanosheet disposed on the sacrificial nanosheet. The semiconductor device includes a gate formed in a direction orthogonal to the plane of the nanosheet stack, with a gate spacer positioned along a sidewall of the gate. The semiconductor device includes an inner spacer liner deposited around the nanosheet stack and the gate spacer. A first etching of the inner spacer liner is configured to produce an outer profile of the inner spacer liner, the outer profile having a substantially flat side section relative to an edge of the channel nanosheet. A second etching of the inner spacer liner is configured to remove substantially all material of the inner spacer liner from the edge of the channel nanosheet.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicolas Loubet, Julien Frougier, Wenyu Xu, Zhenxing Bi
  • Patent number: 10580771
    Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: March 3, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Qing Liu, Prasanna Khare, Nicolas Loubet
  • Patent number: 10573755
    Abstract: A method of fabricating a nanosheet semiconductor device includes depositing sacrificial material on a layer of silicon germanium (SiGe) above a substrate. A thickness of the sacrificial material is more than a thickness of the layer of SiGe. The method also includes forming nanosheet fins comprising alternating silicon (Si) nanosheets and silicon germanium (SiGe) layers on the sacrificial material, undercutting the SiGe layers to form divots, and forming a dummy gate structure above each of the nanosheet fins. A first liner is deposited to fill the divots and cover the nanosheet fins and the dummy gate structure. The sacrificial material and the first liner material are removed. The method also includes encapsulating the nanosheet fins and the dummy gate structure with a conformal liner, and performing an oxide fill to create a buried oxide (BOX) isolation between subsequently formed source and drain regions between the nanosheet fins and the substrate.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: February 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Julien Frougier, Kangguo Cheng, Nicolas Loubet, Ruilong Xie
  • Patent number: 10566443
    Abstract: A substrate structure having a set of nanosheet layers and a set of sacrificial layers stacked upon a substrate is received and a dummy gate is formed upon the nanosheet layers and the sacrificial layers. A portion of a subset of the set of sacrificial layers and a subset of the set of nanosheet layers is etched. A portion of a subset of the subset of sacrificial layers is etched to create divots within the sacrificial layers. A divot fill layer is deposited. The divot fill layer is etched to form an inner spacer between the nanosheet layers. A source/drain region is formed adjacent to the nanosheet layers and the divots. A remaining portion of the subset of the sacrificial layers is removed. The subset of the nanosheet layers is etched to a desired channel thickness producing faceted surfaces between the subset of nanosheet layers and the inner spacer.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Nicolas Loubet, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10566436
    Abstract: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, a trench contact formed on and in contact with the source/drain, and a source/drain contact formed on an in contact with the trench contact. A recess is formed in a portion of the source/drain contact using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the source/drain contact. A metallization layer is formed in contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Julien Frougier, Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng
  • Publication number: 20200051872
    Abstract: Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.
    Type: Application
    Filed: August 9, 2018
    Publication date: February 13, 2020
    Inventors: Jing Guo, Ekmini A. De Silva, Nicolas Loubet, Indira Seshadri, Nelson Felix
  • Publication number: 20200052107
    Abstract: A method of forming a nanosheet device is provided. The method includes forming a nanosheet channel layer stack and dummy gate structure on a substrate. The method further includes forming a curved recess in the substrate surface adjacent to the nanosheet channel layer stack. The method further includes depositing a protective layer on the curved recess, dummy gate structure, and exposed sidewall surfaces of the nanosheet layer stack, and removing a portion of the protective layer on the curved recess to form a downward-spiked ridge around the rim of the curved recess. The method further includes extending the curved recess deeper into the substrate to form an extended recess, and forming a sacrificial layer at the surface of the extended recess in the substrate.
    Type: Application
    Filed: August 13, 2018
    Publication date: February 13, 2020
    Inventors: Fee Li Lie, Mona Ebrish, Ekmini A. De Silva, Indira Seshadri, Gauri Karve, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Nicolas Loubet
  • Publication number: 20200044053
    Abstract: A substrate structure having a set of nanosheet layers and a set of sacrificial layers stacked upon a substrate is received and a dummy gate is formed upon the nanosheet layers and the sacrificial layers. A portion of a subset of the set of sacrificial layers and a subset of the set of nanosheet layers is etched. A portion of a subset of the subset of sacrificial layers is etched to create divots within the sacrificial layers. A divot fill layer is deposited. The divot fill layer is etched to form an inner spacer between the nanosheet layers. A source/drain region is formed adjacent to the nanosheet layers and the divots. A remaining portion of the subset of the sacrificial layers is removed. The subset of the nanosheet layers is etched to a desired channel thickness producing faceted surfaces between the subset of nanosheet layers and the inner spacer.
    Type: Application
    Filed: October 11, 2019
    Publication date: February 6, 2020
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Nicolas Loubet, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Publication number: 20200044057
    Abstract: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.
    Type: Application
    Filed: October 9, 2019
    Publication date: February 6, 2020
    Applicant: International Business Machines Corporation
    Inventors: Julien Frougier, Ruilong Xie, Steven Bentley, Kangguo Cheng, NICOLAS LOUBET, PIETRO MONTANINI