Patents by Inventor Nidhi Nidhi

Nidhi Nidhi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10964690
    Abstract: Techniques are disclosed for forming semiconductor structures including resistors between gates on self-aligned gate edge architecture. A semiconductor structure includes a first semiconductor fin extending in a first direction, and a second semiconductor fin adjacent to the first semiconductor fin, extending in the first direction. A first gate structure is disposed proximal to a first end of the first semiconductor fin and over the first semiconductor fin in a second direction, orthogonal to the first direction, and a second gate structure is disposed proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction. A first structure comprising isolation material is centered between the first and second semiconductor fins. A second structure comprising resistive material is disposed in the first structure, the second structure extending at least between the first gate structure and the second gate structure.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Roman W. Olac-Vaw, Walid M. Hafez, Chia-Hong Jan, Hsu-Yu Chang, Neville L. Dias, Rahul Ramaswamy, Nidhi Nidhi, Chen-Guan Lee
  • Publication number: 20210074642
    Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.
    Type: Application
    Filed: April 1, 2016
    Publication date: March 11, 2021
    Inventors: Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi, Chia-Hong Jan
  • Patent number: 10903372
    Abstract: Metal-oxide-polysilicon tunable resistors and methods of fabricating metal-oxide-polysilicon tunable resistors are described. In an example, a tunable resistor includes a polysilicon resistor structure disposed above a substrate. A gate oxide layer is disposed on the polysilicon resistor structure. A metal gate layer is disposed on the gate oxide layer.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi, Chia-Hong Jan
  • Publication number: 20200395358
    Abstract: Disclosed herein are IC structures, packages, and devices that include self-aligned III-N transistors monolithically integrated on the same support structure or material (e.g., a substrate, a die, or a chip) as extended-drain III-N transistors. Self-aligned III-N transistors may provide a viable approach to implementing digital logic circuits, e.g., to implementing enhancement mode transistors, on the same support structure with extended-drain III-N transistors which may be used as high-power transistors used to implement various RF components, thus enabling integration of III-N devices with digital logic.
    Type: Application
    Filed: June 17, 2019
    Publication date: December 17, 2020
    Applicant: Intel Corporation
    Inventors: Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta, Paul B. Fischer, Nidhi Nidhi, Rahul Ramaswamy, Johann Christian Rode, Walid M. Hafez
  • Publication number: 20200373421
    Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistor arrangements that may reduce nonlinearity of off-state capacitance of the III-N transistors. In various aspects, III-N transistor arrangements limit the extent of access regions of the transistors, compared to conventional implementations, which may limit the depletion of the access regions. Due to the limited extent of the depletion regions of a transistor, the off-state capacitance may exhibit less variability in values across different gate-source voltages and, hence, exhibit a more linear behavior during operation.
    Type: Application
    Filed: May 22, 2019
    Publication date: November 26, 2020
    Applicant: Intel Corporation
    Inventors: Nidhi Nidhi, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer, Rahul Ramaswamy, Walid M. Hafez, Johann Christian Rode
  • Publication number: 20200373297
    Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistor-based cascode arrangements that may simultaneously realize enhancement mode transistor operation and high voltage capability. In one aspect, an IC structure includes a source region, a drain region, an enhancement mode III-N transistor, and a depletion mode III-N transistor, where each of the transistors includes a first and a second source or drain (S/D) terminals. The transistors are arranged in a cascode arrangement in that the first S/D terminal of the enhancement mode III-N transistor is coupled to the source region, the second S/D terminal of the enhancement mode III-N transistor is coupled to the first S/D terminal of the depletion mode III-N transistor, and the second S/D terminal of the depletion mode III-N transistor is coupled to the drain region.
    Type: Application
    Filed: May 22, 2019
    Publication date: November 26, 2020
    Applicant: Intel Corporation
    Inventors: Nidhi Nidhi, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer, Rahul Ramaswamy, Walid M. Hafez, Johann Christian Rode
  • Publication number: 20200335526
    Abstract: Disclosed herein are IC structures, packages, and devices that include Si-based semiconductor material stack monolithically integrated on the same support structure as non-Si transistors or other non-Si-based devices. In some aspects, the Si-based semiconductor material stack may be provided by semiconductor regrowth over an insulator material. Providing a Si-based semiconductor material stack monolithically integrated on the same support structure as non-Si based devices may provide a viable approach to integrating Si-based transistors with non-Si technologies because the Si-based semiconductor material stack may serve as a foundation for forming Si-based transistors.
    Type: Application
    Filed: April 22, 2019
    Publication date: October 22, 2020
    Applicant: Intel Corporation
    Inventors: Nidhi Nidhi, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer, Rahul Ramaswamy, Walid M. Hafez, Johann Christian Rode
  • Publication number: 20200335590
    Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors implementing various means by which their threshold voltage it tuned. In some embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included in a gate stack of the transistor. In other embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included between a gate stack and a III-N channel stack of the transistor. Including doped semiconductor or fixed charge materials either in the gate stack or between the gate stack and the III-N channel stack of III-N transistors adds charges, which affects the amount of 2DEG and, therefore, affects the threshold voltages of these transistors.
    Type: Application
    Filed: April 22, 2019
    Publication date: October 22, 2020
    Applicant: Intel Corporation
    Inventors: Nidhi Nidhi, Marko Radosavljevic, Sansaptak Dasgupta, Yang Cao, Han Wui Then, Johann Christian Rode, Rahul Ramaswamy, Walid M. Hafez, Paul B. Fischer
  • Publication number: 20200335592
    Abstract: Disclosed herein are IC structures, packages, and devices that include transistors, e.g., III-N transistors, having a source region, a drain region (together referred to as “source/drain” (S/D) regions), and a gate stack. In one aspect, a contact to at least one of the S/D regions of a transistor may have a width that is smaller than a width of the S/D region. In another aspect, a contact to a gate electrode material of the gate stack of a transistor may have a width that is smaller than a width of the gate electrode material. Reducing the width of contacts to S/D regions or gate electrode materials of a transistor may reduce the overlap area between various pairs of these contacts, which may, in turn, allow reducing the off-state capacitance of the transistor. Reducing the off-state capacitance of III-N transistors may advantageously allow increasing their switching frequency.
    Type: Application
    Filed: April 18, 2019
    Publication date: October 22, 2020
    Applicant: Intel Corporation
    Inventors: Rahul Ramaswamy, Nidhi Nidhi, Walid M. Hafez, Johann Christian Rode, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
  • Publication number: 20200312961
    Abstract: Disclosed herein are IC structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N devices, e.g., III-N transistors. In various aspects, TFTs integrated with III-N transistors have a channel and source/drain materials that include one or more of a crystalline material, a polycrystalline semiconductor material, or a laminate of crystalline and polycrystalline materials. In various aspects, TFTs integrated with III-N transistors are engineered to include one or more of 1) graded dopant concentrations in their source/drain regions, 2) graded dopant concentrations in their channel regions, and 3) thicker and/or composite gate dielectrics in their gate stacks.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Applicant: Intel Corporation
    Inventors: Han Wui Then, Nidhi Nidhi, Paul B. Fischer, Rahul Ramaswamy, Walid M. Hafez, Samuel Jack Beach, Xiaojun Weng, Johann Christian Rode, Marko Radosavljevic, Sansaptak Dasgupta
  • Publication number: 20200303371
    Abstract: Disclosed herein are integrated circuit structures, packages, and devices that include resistors and/or capacitors which may be provided on the same substrate/die/chip as III-N devices, e.g., III-N transistors. An integrated circuit structure, comprising a base structure comprising a III-N material, the base structure having a conductive region of a doped III-N material. The IC structure further comprises a first contact element, including a first conductive element, a dielectric element, and a second conductive element, wherein the dielectric element is between the first conductive element and the second conductive element, and wherein the first conductive element is between the conductive region and the dielectric element. The IC structure further comprises a second contact element electrically coupled to the first contact element via the conductive region.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Applicant: Intel Corporation
    Inventors: Nidhi Nidhi, Rahul Ramaswamy, Han Wui Then, Marko Radosavljevic, Johann Christian Rode, Paul B. Fischer, Walid M. Hafez
  • Publication number: 20200295172
    Abstract: Disclosed herein are IC structures, packages, and device assemblies with III-N transistors that include additional materials, referred to herein as “stressor materials,” which may be selectively provided over portions of polarization materials to locally increase or decrease the strain in the polarization material. Providing a compressive stressor material may decrease the tensile stress imposed by the polarization material on the underlying portion of the III-N semiconductor material, thereby decreasing the two-dimensional electron gas (2DEG) and increasing a threshold voltage of a transistor. On the other hand, providing a tensile stressor material may increase the tensile stress imposed by the polarization material, thereby increasing the 2DEG and decreasing the threshold voltage. Providing suitable stressor materials enables easier and more accurate control of threshold voltage compared to only relying on polarization material recess.
    Type: Application
    Filed: March 11, 2019
    Publication date: September 17, 2020
    Applicant: Intel Corporation
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Nidhi Nidhi, Rahul Ramaswamy, Paul B. Fischer, Walid M. Hafez, Johann Christian Rode
  • Publication number: 20200294932
    Abstract: IC structures that include transmission line structures to be integrated with III-N devices are disclosed. An example transmission line structure includes a transmission line of an electrically conductive material provided above a stack of a III-N semiconductor material and a polarization material. The transmission line structure further includes means for reducing electromagnetic coupling between the line and charge carriers present below the interface of the polarization material and the III-N semiconductor material. In some embodiments, said means include a shield material of a metal or a doped semiconductor provided over portions of the polarization material that are under the transmission line. In other embodiments, said means include dopant atoms implanted into the portions of the polarization material that are under the transmission line, and into at least an upper portion of the III-N semiconductor material under such portions of the polarization material.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 17, 2020
    Applicant: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Nidhi Nidhi, Paul B. Fischer, Rahul Ramaswamy, Walid M. Hafez, Johann Christian Rode
  • Publication number: 20200279932
    Abstract: Disclosed herein are IC structures, packages, and devices that include planar III-N transistors with wrap-around gates and/or one or more wrap-around source/drain (S/D) contacts. An example IC structure includes a support structure (e.g., a substrate) and a planar III-N transistor. The transistor includes a channel stack of a III-N semiconductor material and a polarization material, provided over the support structure, a pair of S/D regions provided in the channel stack, and a gate stack of a gate dielectric material and a gate electrode material provided over a portion of the channel stack between the S/D regions, where the gate stack at least partially wraps around an upper portion of the channel stack.
    Type: Application
    Filed: March 1, 2019
    Publication date: September 3, 2020
    Applicant: Intel Corporation
    Inventors: Nidhi Nidhi, Rahul Ramaswamy, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Johann Christian Rode, Paul B. Fischer, Walid M. Hafez
  • Publication number: 20200273860
    Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same support structure as non-III-N transistors (e.g., Si-based transistors), using semiconductor regrowth. In one aspect, a non-III-N transistor may be integrated with an III-N transistor by depositing a III-N material, forming an opening in the III-N material, and epitaxially growing within the opening a semiconductor material other than the III-N material. Since the III-N material may serve as a foundation for forming III-N transistors, while the non-III-N material may serve as a foundation for forming non-III-N transistors, such an approach advantageously enables implementation of both types of transistors on a single support structure. Proposed integration may reduce costs and improve performance by enabling integrated digital logic solutions for III-N transistors and by reducing losses incurred when power is routed off chip in a multi-chip package.
    Type: Application
    Filed: February 22, 2019
    Publication date: August 27, 2020
    Applicant: Intel Corporation
    Inventors: Sansaptak Dasgupta, Johann Christian Rode, Han Wui Then, Marko Radosavljevic, Paul B. Fischer, Nidhi Nidhi, Rahul Ramaswamy, Sandrine Charue-Bakker, Walid M. Hafez
  • Publication number: 20200266291
    Abstract: Disclosed herein are IC structures that implement field plates for III-N transistors in a form of electrically conductive structures provided in a III-N semiconductor material below the polarization layer (i.e., at the “backside” of an IC structure). In some embodiments, such a field plate may be implemented as a through-silicon via (TSV) extending from the back/bottom face of the substrate towards the III-N semiconductor material. Implementing field plates at the backside may provide a viable approach to changing the distribution of electric field at a transistor drain and increasing the breakdown voltage of an III-N transistor without incurring the large parasitic capacitances associated with the use of metal field plates provided above the polarization material. In addition, backside field plates may serve as a back barrier for advantageously reducing drain-induced barrier lowering.
    Type: Application
    Filed: February 14, 2019
    Publication date: August 20, 2020
    Applicant: Intel Corporation
    Inventors: Johann Christian Rode, Nidhi Nidhi, Rahul Ramaswamy, Han Wui Then, Walid M. Hafez
  • Publication number: 20200227407
    Abstract: Disclosed herein are IC structures, packages, and devices that include polysilicon resistors, monolithically integrated on the same substrate/die/chip as III-N transistors. An example IC structure includes an III-N semiconductor material provided over a support structure, a III-N transistor provided over a first portion of the III-N material, and a polysilicon resistor provided over a second portion of the III-N material. Because the III-N transistor and the polysilicon resistor are both provided over a single support structure, they may be referred to as “integrated” transistors. Because the III-N transistor and the polysilicon resistor are provided over different portions of the III-N semiconductor material, and, therefore, over different portion of the support structure, their integration may be referred to as “side-by-side” integration.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventors: Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta, Paul B. Fischer, Nidhi Nidhi, Rahul Ramaswamy, Johann Christian Rode, Walid M. Hafez
  • Publication number: 20200219772
    Abstract: An integrated circuit structure and methodologies of forming same. In an embodiment, the integrated circuit structure includes a transistor gate structure in a first region of semiconductor material and a diode in a second region of the semiconductor material. The gate structure has a gate electrode of conductive material with a liner along sides and a bottom of the gate electrode. The gate electrode has a gate length less than a threshold dimension value. The diode includes a body of the conductive material in contact with the semiconductor material and includes the liner along sides of the body of conductive material. The body of conductive material has a lateral dimension greater than the threshold dimension value. The liner can include, for example, a gate dielectric and a diffusion barrier in some embodiments. In other embodiments, the liner is the gate dielectric (without any diffusion barrier).
    Type: Application
    Filed: January 3, 2019
    Publication date: July 9, 2020
    Applicant: INTEL CORPORATION
    Inventors: RAHUL RAMASWAMY, NIDHI NIDHI, WALID M. HAFEZ, JOHANN C. RODE, PAUL FISCHER, HAN WUI THEN, MARKO RADOSAVLJEVIC, SANSAPTAK DASGUPTA
  • Publication number: 20200219986
    Abstract: Disclosed herein are IC structures, packages, and devices assemblies that use ions or fixed charge to create field plate structures which are embedded in a dielectric material between gate and drain electrodes of a transistor, ion- or fixed charge-based field plate structures may provide viable approaches to changing the distribution of electric field at a transistor drain to increase the breakdown voltage of a transistor without incurring the large parasitic capacitances associated with the use of metal field plates. In one aspect, an IC structure includes a transistor, a dielectric material between gate and drain electrodes of the transistor, and an ion- or fixed charge-based region within the dielectric material, between the gate and the drain electrodes. Such an ion- or fixed charge-based region realizes an ion- or fixed charge-based field plate structure. Optionally, the IC structure may include multiple ion- or fixed charge-based field plate structures.
    Type: Application
    Filed: January 8, 2019
    Publication date: July 9, 2020
    Applicant: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Glenn A. Glass, Sansaptak Dasgupta, Nidhi Nidhi, Paul B. Fischer, Rahul Ramaswamy, Walid M. Hafez, Johann Christian Rode
  • Publication number: 20200203484
    Abstract: A transistor is disclosed. The transistor includes a substrate, a superlattice structure that includes a plurality of heterojunction channels, and a gate that extends to one of the plurality of heterojunction channels. The transistor also includes a source adjacent a first side of the superlattice structure and a drain adjacent a second side of the superlattice structure.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Inventors: Nidhi NIDHI, Rahul RAMASWAMY, Sansaptak DASGUPTA, Han Wui THEN, Marko RADOSAVLJEVIC, Johann C. RODE, Paul B. FISCHER, Walid M. HAFEZ