Patents by Inventor Nidhi Sinha

Nidhi Sinha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9494969
    Abstract: An on-board reset circuit for a system-on-chip (SOC) addresses the problem of meta-stability in flip-flops on asynchronous reset that arises when different power domains or reset domains receive resets from different sources. To ameliorate the problem, a reset signal is asserted and de-asserted while the clocks are gated. The clocks are re-instated for a minimum period of time following assertion (or de-assertion) so that logic having synchronous reset can also receive the reset.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: November 15, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Aniruddha Gupta, Akshay K. Pathak, Garima Sharda, Nidhi Sinha
  • Patent number: 9476937
    Abstract: An integrated circuit (IC) operable in functional and debug modes includes a debug enable circuit, a pad control register, a debug circuit, a pad configuration register, and an input/output (IO) pad. The debug circuit receives a functional signal from a circuit monitoring circuit, a reference signal, a debug control signal from the debug enable circuit, and pull-enable control and pull-type select control signals from the pad control register, and generates pull-enable and pull-type select signals. The pad configuration register receives the pull-enable and pull-type select signals and configures the IO pad in one of logic low, logic high, and high impedance states. When the IO pad is in either of the logic high and low states longer than a predetermined time period, then the IO pad indicates that the IC is held in a reset phase of a reset sequence.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: October 25, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Garima Sharda, Sunny Gupta, Akshay K. Pathak, Nidhi Sinha
  • Publication number: 20160109515
    Abstract: An integrated circuit (IC) operable in functional and debug modes includes a debug enable circuit, a pad control register, a debug circuit, a pad configuration register, and an input/output (IO) pad. The debug circuit receives a functional signal from a circuit monitoring circuit, a reference signal, a debug control signal from the debug enable circuit, and pull-enable control and pull-type select control signals from the pad control register, and generates pull-enable and pull-type select signals. The pad configuration register receives the pull-enable and pull-type select signals and configures the IO pad in one of logic low, logic high, and high impedance states. When the IO pad is in either of the logic high and low states longer than a predetermined time period, then the IO pad indicates that the IC is held in a reset phase of a reset sequence.
    Type: Application
    Filed: October 15, 2014
    Publication date: April 21, 2016
    Inventors: Garima Sharda, Sunny Gupta, Akshay K. Pathak, Nidhi Sinha
  • Publication number: 20160048155
    Abstract: An on-board reset circuit for a system-on-chip (SOC) addresses the problem of meta-stability in flip-flops on asynchronous reset that arises when different power domains or reset domains receive resets from different sources. To ameliorate the problem, a reset signal is asserted and de-asserted while the clocks are gated. The clocks are re-instated for a minimum period of time following assertion (or de-assertion) so that logic having synchronous reset can also receive the reset.
    Type: Application
    Filed: August 12, 2014
    Publication date: February 18, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Anirudhha Gupta, Akshay K. Pathak, Garima Sharda, Nidhi Sinha