Patents by Inventor Nikolaos Papandreou
Nikolaos Papandreou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11656792Abstract: A data storage system provides persistent storage in bulk non-volatile memory. A controller of the data storage system receives a host write command and buffers associated host write data in both a first write cache in non-volatile memory and a mirrored second write cache in volatile memory. The controller destages the host write data to the bulk non-volatile memory from the second write cache but not the first write cache. The controller services relocation write commands requesting data relocation within the bulk non-volatile memory by reference to the second write cache. Servicing the relocation write commands includes buffering relocation write data in the second write cache but not the first write cache and destaging the relocation write data to the bulk non-volatile memory from the second write cache.Type: GrantFiled: June 29, 2021Date of Patent: May 23, 2023Assignee: International Business Machines CorporationInventors: Roman Alexander Pletka, Timothy J. Fisher, Adalberto Guillermo Yanes, Nikolaos Papandreou, Radu Ioan Stoica, Charalampos Pozidis, Nikolas Ioannou
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Publication number: 20230108194Abstract: A non-volatile memory includes a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages. A controller of the non-volatile memory issues a command to perform a programming pass for a physical page among the multiple physical pages. The controller determines whether or not the programming pass took less than a minimum threshold time and no program fail status indication was received. Based on determining the programming pass took less than a minimum threshold time and no program fail status indication was received, the controller detects an under-programming error and performs mitigation for the detected under-programming error.Type: ApplicationFiled: October 6, 2021Publication date: April 6, 2023Inventors: Nikolaos Papandreou, ROMAN ALEXANDER PLETKA, Radu Ioan Stoica, Nikolas Ioannou, Charalampos Pozidis, Timothy J. Fisher, Aaron Daniel Fry
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Patent number: 11621078Abstract: The invention is notably directed to a computer-implemented method for normalizing medical images, e.g., whole slide images. This method includes steps performed for each image of a first subset of images of a dataset. Actual quantities are estimated for each image, including actual stain vectors and, possibly, robust maximum stain concentrations (typically hematoxylin and eosin stain vectors and concentrations). The actual quantities estimated are assessed by comparing them to reference data based on reference quantities estimated for one or more images of a second subset of images of the dataset, where the second subset of images differ from the first subset of images. The reference quantities include reference stain vectors. For each image, either the actual quantities or the reference quantities for the dataset are selected as effective quantities, based on an outcome of the previous assessment of the actual quantities. Each image is then normalized.Type: GrantFiled: March 18, 2020Date of Patent: April 4, 2023Assignee: International Business Machines CorporationInventors: Nikolaos Papandreou, Sonali Andani, Andreea Anghel, Milos Stanisavljevic
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Publication number: 20230057271Abstract: A data storage system includes a plurality of storage devices organized as a redundant array of inexpensive disks (RAID) storage array and a RAID controller. The RAID controller monitors the plurality of storage devices in the RAID storage array. The RAID controller also detects that a host read request of a host has a latency exceeding a latency threshold. Based on the monitoring, the RAID controller determines whether a proactive rebuild of a data requested by the host read request in absence of a data error would likely be beneficial to performance. Based on determining that a proactive rebuild of the data requested by the host read request would likely be beneficial to performance, the RAID controller initiates the proactive rebuild of the data and sends the requested data to the host.Type: ApplicationFiled: August 18, 2021Publication date: February 23, 2023Inventors: RADU IOAN STOICA, NIKOLAS IOANNOU, ROMAN ALEXANDER PLETKA, NIKOLAOS PAPANDREOU, CHARALAMPOS POZIDIS
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Patent number: 11567673Abstract: A data storage system includes a plurality of storage devices organized as a redundant array of inexpensive disks (RAID) storage array and a RAID controller. The RAID controller monitors the plurality of storage devices in the RAID storage array. The RAID controller also detects that a host read request of a host has a latency exceeding a latency threshold. Based on the monitoring, the RAID controller determines whether a proactive rebuild of a data requested by the host read request in absence of a data error would likely be beneficial to performance. Based on determining that a proactive rebuild of the data requested by the host read request would likely be beneficial to performance, the RAID controller initiates the proactive rebuild of the data and sends the requested data to the host.Type: GrantFiled: August 18, 2021Date of Patent: January 31, 2023Assignee: International Business Machines CorporationInventors: Radu Ioan Stoica, Nikolas Ioannou, Roman Alexander Pletka, Nikolaos Papandreou, Charalampos Pozidis
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Publication number: 20230010632Abstract: A non-volatile memory includes a plurality of physical blocks each including a respective plurality of cells, where each cell is individually capable of storing multiple bits of data. A controller for the non-volatile memory maintains dynamically resizable pools of physical blocks, including at least a low-density pool of physical blocks in which cells are configured to store a fewer number of bits and a high-density pool of physical blocks in which cells are configured to store a greater number of bits. The controller detects an imbalance in utilization between the low-density and high-density pools and, based on detection of the pool imbalance, restricts data placement in the low-density pool, enables garbage collection from the low-density pool back into the low-density pool to compact the low-density pool, and re-enables data placement to the low-density pool based on availability of a threshold number of free physical blocks in the low-density pool.Type: ApplicationFiled: July 6, 2021Publication date: January 12, 2023Inventors: ROMAN ALEXANDER PLETKA, AARON DANIEL FRY, NIKOLAOS PAPANDREOU, RADU IOAN STOICA, CHARALAMPOS POZIDIS, NIKOLAS IOANNOU
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Publication number: 20220415424Abstract: A memory controller receives a multi-plane read request and identifies a set of actual read offsets for a set of pages in the multi-plane read request. The memory controller calculates a common read offset using the set of actual read offsets. The memory controller calculates an offset difference for. Each page. Each offset difference reflects the difference between an actual read offset for that page and the common read offset. The memory controller compares a particular page's offset difference to an offset difference threshold. The memory controller categorizes, based on the comparing, a first subset of pages from the set of pages into a single plane group and a second subset of pages from the set of pages into a multi-plane group. The memory controller performs a multi-plane read on the multi-plane group.Type: ApplicationFiled: June 23, 2021Publication date: December 29, 2022Inventors: Nikolaos Papandreou, Nikolas Ioannou, Roman Alexander Pletka, Radu Ioan Stoica, Charalampos Pozidis, Timothy J. Fisher, Andrew D. Walls
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Publication number: 20220413762Abstract: A data storage system provides persistent storage in bulk non-volatile memory. A controller of the data storage system receives a host write command and buffers associated host write data in both a first write cache in non-volatile memory and a mirrored second write cache in volatile memory. The controller destages the host write data to the bulk non-volatile memory from the second write cache but not the first write cache. The controller services relocation write commands requesting data relocation within the bulk non-volatile memory by reference to the second write cache. Servicing the relocation write commands includes buffering relocation write data in the second write cache but not the first write cache and destaging the relocation write data to the bulk non-volatile memory from the second write cache.Type: ApplicationFiled: June 29, 2021Publication date: December 29, 2022Inventors: ROMAN ALEXANDER PLETKA, TIMOTHY J. FISHER, ADALBERTO GUILLERMO YANES, NIKOLAOS PAPANDREOU, RADU IOAN STOICA, CHARALAMPOS POZIDIS, NIKOLAS IOANNOU
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Patent number: 11474920Abstract: Data protection systems and techniques that include: receiving data for storage in a non-volatile memory (NVM) array having a total number of physical packages that includes a number of spare physical packages, wherein each one of the physical packages is mapped to one of a plurality of logical packages; storing a respective portion of component codewords on the non-spare physical packages; and in response to one of the non-spare physical packages failing, dynamically remapping the failed physical package to one of the logical packages mapped to one of the available spare physical packages. In an aspect, reading at least the failed physical package and inserting virtual zeros into the respective portion of the component codewords corresponding to the failed physical package; performing erasure decoding to recover the data from the failed package; and rewriting the recovered data from the failed package into the one of the available spare physical packages.Type: GrantFiled: March 31, 2020Date of Patent: October 18, 2022Assignee: International Business Machines CorporationInventors: Charalampos Pozidis, Thomas Mittelholzer, Nikolaos Papandreou, Milos Stanisavljevic
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Publication number: 20220198281Abstract: An approach of accelerating inferences based on decision trees based on accessing one or more decision trees, wherein each decision tree of the decision trees accessed comprises decision tree nodes, including nodes grouped into one or more supersets of nodes designed for joint execution. For each decision tree of the decision trees accessed, the nodes are executed to obtain an outcome for the one or more decision trees, respectively. For each superset of the one or more supersets of said each decision tree, the nodes of each superset are jointly executed by: loading attributes of the nodes of each superset in a respective cache line of the cache memory processing said attributes from the respective cache line until an inference result is returned based on the one or more outcomes.Type: ApplicationFiled: December 18, 2020Publication date: June 23, 2022Inventors: Jan Van Lunteren, Nikolas Ioannou, Nikolaos Papandreou, Thomas Parnell, Andreea Anghel, Charalampos Pozidis
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Patent number: 11360903Abstract: A computer-implemented method, according to one approach, includes: determining a current read heat value of each logical page which corresponds to write requests that have accumulated in a destage buffer. Each of the write requests is assigned to a respective write queue based on the current read heat value of each logical page which corresponds to the write requests. Moreover, each of the write queues correspond to a different page stripe which includes physical pages, the physical pages included in each of the respective page stripes being of a same type. Other systems, methods, and computer program products are described in additional approaches.Type: GrantFiled: February 3, 2021Date of Patent: June 14, 2022Assignee: International Business Machines CorporationInventors: Roman Alexander Pletka, Timothy Fisher, Aaron Daniel Fry, Nikolaos Papandreou, Nikolas Ioannou, Sasa Tomic, Radu Ioan Stoica, Charalampos Pozidis, Andrew D. Walls
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Publication number: 20220180211Abstract: According to one embodiment, a method, computer system, and computer program product for training a cognitive model that involves one or more decision trees as base learners is provided. The present invention may include constructing, by a tree building algorithm, the one or more decision trees, wherein the constructing further comprises associating one or more training examples with one or more leaf nodes of the one or more decision trees and iteratively running a breadth-first search tree builder on one or more of the decision trees to perform one or more tree building operations; and training the cognitive model based on the one or more decision trees.Type: ApplicationFiled: December 4, 2020Publication date: June 9, 2022Inventors: Nikolas Ioannou, Thomas Parnell, Andreea Anghel, Nikolaos Papandreou, Charalampos Pozidis
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Patent number: 11334492Abstract: A computer-implemented method, according to one embodiment, is for calibrating read voltages for a block of memory. The computer-implemented method includes: determining a calibration read mode of the block, and using the calibration read mode to determine whether pages in the block should be read using full page read operations. In response to determining that the pages in the block should not be read using full page read operations, a current value of a partial page read indicator for the block is determined. The block is further calibrated by reading only a portion of each page in the block, where the current value of the partial page read indicator determines which portion of each respective page in the block is read. Moreover, the current value of the partial page read indicator is incremented.Type: GrantFiled: October 24, 2019Date of Patent: May 17, 2022Assignee: International Business Machines CorporationInventors: Nikolaos Papandreou, Charalampos Pozidis, Roman Alexander Pletka, Sasa Tomic, Nikolas Ioannou, Radu Ioan Stoica
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Patent number: 11314595Abstract: A RAID controller periodically collects an indication of a current compression ratio achieved by each of a plurality of storage devices within the RAID. The RAID controller determines a placement of data and the parity information within at least one of the plurality of storage devices according to at least one of a plurality of factors associated with the current compression ratio. The RAID controller writes the data and the parity information to the at least one of the plurality of storage devices according to the determined placement.Type: GrantFiled: December 21, 2020Date of Patent: April 26, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Roman Alexander Pletka, Sasa Tomic, Timothy Fisher, Nikolaos Papandreou, Nikolas Ioannou, Aaron Fry
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Patent number: 11302403Abstract: A computer-implemented method, according to one approach, is for calibrating read voltages associated with a block of memory having more than one word-line therein. The computer-implemented method includes: for each of the word-lines in the block: calculating an absolute shift value for a reference read voltage associated with the given word-line. A relative shift value is also determined for each of the remaining read voltages associated with the given word-line, and the relative shift values are determined with respect to the reference read voltage. Moreover, each of the read voltages associated with the given word-line are adjusted using the absolute shift value and each of the respective relative shift values.Type: GrantFiled: January 14, 2021Date of Patent: April 12, 2022Assignee: International Business Machines CorporationInventors: Nikolaos Papandreou, Charalampos Pozidis, Nikolas Ioannou, Roman Alexander Pletka, Radu Ioan Stoica, Sasa Tomic, Timothy Fisher, Aaron Daniel Fry
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Patent number: 11264103Abstract: A computer-implemented method, according to one embodiment, includes: determining a current operating state of a block of memory. The block includes more than one type of page therein, and at least one read voltage is associated with each of the page types. The current operating state of the block is further used to produce a hybrid calibration scheme for the block which identifies a first subset of the read voltages, and a second subset of the read voltages. The read voltages in the second subset are further organized in one or more groupings. A unique read voltage offset value is calculated for each of the read voltages in the first subset, and a common read voltage offset value is also calculated for each grouping of read voltages in the second subset.Type: GrantFiled: August 28, 2019Date of Patent: March 1, 2022Assignee: International Business Machines CorporationInventors: Nikolaos Papandreou, Charalampos Pozidis, Nikolas Ioannou, Roman Alexander Pletka, Radu Ioan Stoica, Sasa Tomic, Timothy Fisher, Aaron Daniel Fry, Andrew D. Walls
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Patent number: 11238295Abstract: Processing a digital image in a distributed computing environment comprising a communications network interconnecting two or more computing nodes. A segmentation of the digital image into two or more image segments is determined. For each of the image segments, a number of non-background pixels comprised by the image segment is determined. An assignment of each of the image segments to one of the computing nodes is determined. The determination of the assignment may include balancing, based on the number of non-background pixels determined for each of the image segments, the workload of the assigned computing nodes responsive to processing the image segments. Each of the assigned computing nodes may be caused to process the image segments assigned to the computing node.Type: GrantFiled: March 19, 2019Date of Patent: February 1, 2022Assignee: International Business Machines CorporationInventors: Nikolaos Papandreou, Andreea Anghel, Milos Stanisavljevic, Charalampos Pozidis
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Patent number: 11221911Abstract: A memory controller for recovering data due to transient effects of nonvolatile memory is provided. A memory controller receives a read request for a page stored in the nonvolatile memory. The memory controller issues a first read command. The memory controller records a time stamp for the first read command. In response to a failure during the first read command, the memory controller waits for a delay after the recorded time stamp and the memory controller issues a second read command to the page, wherein the second read command applies a read voltage offset that is dependent on the delay between the first read command and the second read command and at least one other parameter.Type: GrantFiled: October 11, 2019Date of Patent: January 11, 2022Assignee: International Business Machines CorporationInventors: Nikolaos Papandreou, Charalampos Pozidis, Nikolas Ioannou, Roman Alexander Pletka, Sasa Tomic
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Patent number: 11188261Abstract: Aspects of the present invention disclose a method, computer program product, and system for controlling operation of an array of non-volatile memory cells comprising cells which are selectively configurable for single-bit and multibit storage. The method includes a memory controller selectively configuring the array for operation in a hybrid mode, in which the array comprises both cells configured for single-bit storage and cells configured for multibit storage, and a multibit mode in which all cells in the array are configured for multibit storage. The method further includes the memory controller dynamically switching between the hybrid and multibit mode configurations of the array corresponding to array capacity-usage traversing a defined threshold level associated with enhance endurance of the array.Type: GrantFiled: November 18, 2019Date of Patent: November 30, 2021Assignee: International Business Machines CorporationInventors: Nikolaos Papandreou, Roman Alexander Pletka, Radu Ioan Stoica, Nikolas Ioannou, Sasa Tomic, Charalampos Pozidis
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Patent number: 11182089Abstract: A computer-implemented method, according to one embodiment, includes: determining whether a number of blocks included in a first ready-to-use (RTU) queue is in a first range of the first RTU queue. In response to determining that the number of blocks included in the first RTU queue is in the first range, a determination is made as to whether a number of blocks included in a second RTU queue is in a second range of the second RTU queue. Moreover, in response to determining that the number of blocks included in the second RTU queue is not in the second range, valid data is relocated from one of the blocks in a first pool which corresponds to the first RTU queue. The block in the first pool is erased, and transferred from the first pool to the second RTU queue which corresponds to a second pool.Type: GrantFiled: July 1, 2019Date of Patent: November 23, 2021Assignee: International Business Machines.CorporationInventors: Roman Alexander Pletka, Radu Ioan Stoica, Sasa Tomic, Nikolaos Papandreou, Nikolas Ioannou, Aaron Daniel Fry, Timothy Fisher, Charalampos Pozidis, Andrew D. Walls