Patents by Inventor Nikolaus Bott

Nikolaus Bott has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor arrangement
    Patent number: 7498194
    Abstract: The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: March 3, 2009
    Assignee: Infineon Technologies AG
    Inventors: Nikolaus Bott, Oliver Haeberlen, Manfred Kotek, Joost Larik, Josef Maerz, Ralf Otremba
  • Semiconductor Arrangement
    Publication number: 20070178624
    Abstract: The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.
    Type: Application
    Filed: April 11, 2007
    Publication date: August 2, 2007
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Nikolaus Bott, Oliver Haeberlen, Manfred Kotek, Joost Larik, Josef Maerz, Ralf Otremba
  • Semiconductor arrangement
    Patent number: 7233059
    Abstract: The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: June 19, 2007
    Assignee: Infineon Technologies AG
    Inventors: Nikolaus Bott, Oliver Haeberlen, Manfred Kotek, Joost Larik, Josef Maerz, Ralf Otremba
  • Semiconductor arrangement
    Publication number: 20050012215
    Abstract: The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.
    Type: Application
    Filed: May 20, 2004
    Publication date: January 20, 2005
    Inventors: Nikolaus Bott, Oliver Haeberlen, Manfred Kotek, Joost Larik, Josef Maerz, Ralf Otremba