Patents by Inventor Nilesh V. Shah

Nilesh V. Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6275242
    Abstract: An embodiment of a method for terminating direct memory access transfers from system memory to a video device includes completing a current byte transfer from a graphics controller to a video device and then refraining from initiating any further write cycles associated with a DMA transfer to the video device. The graphics controller then allows uninterrupted or atomic read and write cycles to the video device. The graphics controller also completes any current read cycles on a system bus that had previously been initiated. The graphics controller then resets its DMA engine and invalidates all information in a first-in, first-out (FIFO) storage buffer.
    Type: Grant
    Filed: December 31, 1998
    Date of Patent: August 14, 2001
    Assignee: Intel Corporation
    Inventors: Nilesh V. Shah, Andrew E. Roedel, Cliff D. Hall
  • Patent number: 5815167
    Abstract: A computer system, including a graphics controller and a memory controller, employs a Shared Frame Buffer Architecture, and accordingly has a shared memory in the form a bank of DRAMs. The shared memory is accessible by both the memory and graphics controllers. The memory includes a shared DRAM row in which a Shared Frame Buffer (SFB) aperture is defined. An interface selectively provides access to the shared DRAM row by the graphics or memory controller, while providing permanent access to the remaining DRAM rows by the memory controller. This facilitates concurrent access by the graphics controller and the memory controller to the shared DRAM row and to the remaining DRAM rows respectively, in a first memory access scenario. The accessibility of the shared DRAM row by the memory controller, in a second memory access scenario, is also maintained.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: September 29, 1998
    Assignee: Intel Corporation
    Inventors: Manish Muthal, Nilesh V. Shah, Kuljit Bains
  • Patent number: 5655127
    Abstract: A computer system having a responsive low-power mode and a full-power mode of operation. The computer system includes a power consumption controller, a processor and a communication device. The power consumption controller generates an interrupt signal in response to a low power event or a fully operational event. The power consumption controller also generates a clock control signal. The clock control signal is deasserted during the full-power mode of operation and alternatively asserted for a first duration and deasserted for a second duration during the low-power mode of operation. In response to an asserted clock control signal, the processor suppresses the internal clock signal to at least one functional block within the processor and in response to a deasserted clock control signal, the processor transmits the internal clock signal to at least one functional block within the processor.
    Type: Grant
    Filed: March 8, 1996
    Date of Patent: August 5, 1997
    Assignee: Intel Corporation
    Inventors: Jeffrey L. Rabe, Zohar Bogin, Ajay V. Bhatt, James P. Kardach, Nilesh V. Shah
  • Patent number: 5551044
    Abstract: A circuit for controlling interrupt request signal transmission in a computer system. An input receives an interrupt request from an external component. First circuitry coupled to the input generates a signal in response to the interrupt request from the external component. The signal causes a processor to switch to fully operational mode. Second circuitry coupled to the input generates an interrupt request signal to the processor in response to the interrupt request from the external component. A signal processing circuit coupled to the second circuitry suppresses transmission of the interrupt request signal to the processor until the signal is transmitted to the processor.
    Type: Grant
    Filed: December 1, 1994
    Date of Patent: August 27, 1996
    Assignee: Intel Corporation
    Inventors: Nilesh V. Shah, Jeffrey L. Rabe, Zohar Bogin