Abstract: The present invention provides a vortex generator that may be used in systems for separating oil from air oil mixtures. The vortex generator comprises a rotating disk having a rim having a plurality of passages extending through it and a cavity formed by the rotating disk and a cavity wall wherein a vortex is created when there is a flow through the plurality of passages into the cavity.

Abstract: In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.

Abstract: The present method provides annealing of a resistive memory device so as to provide that the device in its erased state has a greatly increased resistance as compared to a prior art approach. The annealing also provides that the device may be erased by application of any of a plurality of electrical potentials within an increased range of electrical potentials as compared to the prior art.

Abstract: A metal sulfide based non-volatile memory device is provided herein. The device is comprised of a substrate, a backplane, a planar memory media including a dense array of metal sulfide based memory cells, and a MEMS probe based actuator. The cells of the memory device are operative to be of two or more states corresponding to various levels of impedance. The MEMS actuator is operable to position micro/nano probes over the appropriate cells to enable reading, writing, and erasing the memory cells by applying a bias voltage.

Abstract: Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.

Abstract: Systems and methods employing at least one constant current source to facilitate programming of an organic memory cell and/or employing at least one constant voltage source to facilitate erasing of a memory device. The present invention is utilized in single memory cell devices and memory cell arrays. Employing a constant current source prevents current spikes during programming and allows accurate control of a memory cell's state during write cycles, independent of the cell's resistance. Employing a constant voltage source provides a stable load for memory cells during erase cycles and allows for accurate voltage control across the memory cell despite large dynamic changes in cell resistance during the process.

Abstract: Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.

Abstract: In a memory device having first and second electrodes and active and passive layers between the electrodes, or a memory device having first and second electrodes and an insulating layer between and in contact with electrodes, the device may be programmed in the ionic mode by applying electrical potential across the electrodes in one direction, and may be programmed in the electronic charge carrier mode by applying electrical potential across electrodes in the opposite direction

Abstract: A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, from higher to lower potential in the forward direction, intended to program the selected memory-diode. During this intended programming, each other memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode can be established by applying an electrical potential across that memory-diode from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array, problems related to current leakage and disturb are avoided.

Abstract: In a method of providing an operating characteristic of a resistive memory device, material of an electrode thereof is selected to in turn provide a selected operating characteristic of the device. The material of the electrode may be reacted with material of an insulating layer of the resistive memory device to form a reaction layer, the selected operating characteristic being dependent on the presence of the reaction layer.

Abstract: In the present method of programming a memory device from an erased state, the memory device includes first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrodes. In the programming method, (i) an electrical potential is applied across the first and second electrodes from higher to lower potential in one direction to reduce the resistance of the memory device, and (ii) an electrical potential is applied across the first and second electrodes from higher to lower potential in the other direction to further reduce the resistance of the memory device.

Abstract: An organic memory device comprising two electrodes having a selectively conductive decay media between the two electrodes provides a capability to control a persistence level for information stored in an organic memory cell. A resistive state of the cell controls a conductive decay rate of the cell. A high and/or low resistive state can provide a fast and/or slow rate of conductive decay. One aspect of the present invention can have a high resistive state equating to an exponential conductive decay rate. Another aspect of the present invention can have a low resistive state equating to a logarithmic conductive decay rate. Yet another aspect relates to control of an organic memory device by determining a power state and setting a resistive state of an organic memory cell based upon a current power state and/or an imminent power state.

Abstract: In modeling material constitutive behavior, a methodology determines tool-chip friction and a position of a stagnation point on a cutting tool. The methodology includes measuring a ratio of cutting force to thrust force and measuring a chip thickness, hch, produced by applying the cutting tool to a material. Initial values are estimated for tool chip friction and position of stagnation. The tool chip friction and position of stagnation are calculated to satisfy a specified relationship. Based on tool chip friction and position of stagnation, material strains, material strain-rates, material temperatures, and material stresses are calculated.

Abstract: System(s) and method(s) of improving and controlling memory cell data retention are disclosed. A particular pulse width and magnitude is generated and applied to a memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes. The current across the memory cell is detected and a lower input pulse is sent to the memory cell. Application of the lower pulse controls the data retention of the memory cell without disturbing the final programming state of the memory cell.

Abstract: Provided herein is method of programming a resistive memory device, the resistive memory device including a first electrode, a second electrode, a passive layer between the first and second electrode, and an active layer between the first and second electrodes. In the programming method, an electrical potential is applied across the first and second electrodes from higher to lower potential in the direction from the active layer to the passive layer so that electronic charge carriers enter the active layer and are held by traps therein. In erasing the memory device, an electrical potential is applied across the first and second electrodes from higher to lower potential in the direction from the passive layer to the active layer so that electronic charge carriers are moved from the active layer.

Abstract: A write-once read-many times memory device is made up of first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrode. The memory device is programmed by providing a charged species from the passive layer into the active layer. The memory device may be programmed to have for the programmed memory device a first erase activation energy. The present method provides for the programmed memory device a second erase activation energy greater than the first erase activation energy.

Abstract: A test system having a feedback loop that facilitates adjusting an output test waveform to a DUT/CUT (Device Under Test/Circuit Under Test) on-the-fly according to changing DUT/CUT parameters. The system includes a tester having an arbitrary waveform generator (AWG) and a data acquisition system (DAS) that monitors the status of the DUT/CUT. The AWG and DAS connect to the DUT/CUT through a feedback loop where the AWG outputs the test waveform to the DUT/CUT, the DAS monitors the DUT/CUT parameters, and the DAS analyzes and communicates changes to the AWG to effect changes in the output waveform, when desired. The AWG builds the output waveform in small slices (or segments) that are assembled together through a process of selection and calibration. The feedback architecture facilitates a number of changes in the output waveform, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform.

Abstract: A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, from higher to lower potential in the forward direction, intended to program the selected memory-diode. During this intended programming, each other memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode can be established by applying an electrical potential across that memory-diode from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array, problems related to current leakage and disturb are avoided.

Abstract: One aspect of the present invention relates to a semiconductor transistor device with an annular gate surrounding, at least in part, a channel that conducts current between a first and second source/drain. Another aspect of the present invention relates to a semiconductor transistor device having an annular gate and containing a channel composed of a polymer material. Yet another aspect of the present invention relates to fabrication of a device utilizing a polymer channel surrounded, at least in part, by an annular gate. Still yet another aspect of the present invention relates to a system with a means to control (and/or amplify) current via an annular gate surrounding a channel which conducts current between a first and second source/drain. Still other aspects of the present invention include devices incorporating the present invention's devices, systems and methods such as computers, memory, handhelds and electronic devices.

Abstract: The present memory structure includes thereof a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor, and a second diode connected to the resistive memory cell and the first conductor, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor.