Patents by Inventor Niraj Gupta

Niraj Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9489342
    Abstract: The system has first, second, third, and fourth subsystems. Each subsystem has first and second multipliers coupled, respectively, to first and second adders. Each multiplier has two inputs. The first adder is coupled to a first output, a first accumulator, and a bit shifter. The bit shifter is coupled to a third adder. The third adder is coupled to a multiplexer. The multiplexer is coupled to a second output and a second accumulator. The second adder is coupled to the third adder and the multiplexer. The first outputs of the first and second subsystems are coupled directly to a fourth adder, the second outputs of the first and second subsystems are coupled directly to a fifth adder, the first outputs of the third and fourth subsystems are coupled directly to a sixth adder, and the second outputs of the third and fourth subsystems are coupled directly to a seventh adder.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: November 8, 2016
    Assignee: Intel Corporation
    Inventors: Niraj Gupta, Karthik N
  • Patent number: 9398297
    Abstract: Techniques related to integral image coding are described herein.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: July 19, 2016
    Assignee: INTEL CORPORATION
    Inventor: Niraj Gupta
  • Publication number: 20160092153
    Abstract: A connected classroom system provides for local and remote control and display of media streams. An instructor may, for instance, direct audio/video streams of the instructor to any number of displays and speakers located within a classroom. The system may send and receive control instructions to and from remote classrooms as well, through a network interface. The control instructions may configure any set of presentation devices in any classroom to reproduce any content originating from any source within any classroom. Accordingly, multiple classrooms located in disparate locations may participate in media exchanges arising from any source, including instructors and individual student seating locations within the classrooms.
    Type: Application
    Filed: August 27, 2015
    Publication date: March 31, 2016
    Inventors: Lisa Kay DeMik, Samir Desai, Kishore Prabhakar Durg, Srinivas Govindaiah, James Allen Glore, Niraj Gupta, William Alfred Jindrich, JR., Bryan Michael McCart, Parag Pande, Damien X. Panketh, David Petricca, Nobby Rajan, Syed Sibgathulla, Surendra Sheshagiri, Gordon Trujillo, Alex Zorba
  • Publication number: 20160063428
    Abstract: An intelligent information delivery system facilitates dynamic interaction with the user's environment, and in certain environments may provide or support digital governance. The intelligent delivery system may make use of a distributed beacon network to accurately determine the user's location within an environment, which may then be leveraged to deliver relevant content to the user. The intelligent delivery system may also facilitate complex interactions between a user of the system and the user's environment.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 3, 2016
    Inventors: Kishore Prabhakar Durg, Niraj Gupta, Ramkumar Kothandaraman, Amit Bahree
  • Patent number: 9245495
    Abstract: Systems, apparatus, articles, and methods are described including operations to generate a weighted look-up-table based at least in part on individual pixel input values within an active block region and on a plurality of contrast compensation functions. A second level compensation may be performed for a center pixel block of the active region based at least in part on the weighted look-up-table.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: January 26, 2016
    Assignee: INTEL CORPORATION
    Inventors: Niraj Gupta, Supratim Pal, Mahesh B. Chappalli, Yi-Jen Chiu, Hong Jiang
  • Patent number: 9158498
    Abstract: Systems, apparatus and methods are described related to optimizing fixed point divide.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: October 13, 2015
    Assignee: INTEL CORPORATION
    Inventor: Niraj Gupta
  • Publication number: 20150187042
    Abstract: Methods and systems may synchronize workloads across local thread groups. The methods and systems may provide for receiving, at a graphics processor, a workload from a host processor and receiving, at a plurality of processing elements, a plurality of threads that from one or more local thread groups. Additionally, the processing of the workload may be synchronized across the one or more thread groups. In one example, the global barrier determines that all threads across the thread groups have been completed without polling.
    Type: Application
    Filed: December 8, 2014
    Publication date: July 2, 2015
    Applicant: Intel Corporation
    Inventor: Niraj Gupta
  • Publication number: 20150186458
    Abstract: Systems and methods may provide feature matching in objection-recognition applications. The systems and methods may determine various features of an object and determine what type of object to which the features correspond. The systems and methods may also detect objects within a database and extracts vectors based on unique features of the objects. The extracted vectors may be stored in a memory such as a buffer. The extracted vectors may be used to match against a database of objects of interest or test vectors. Features within the objects may then be quickly and efficiently determined based on the best matches between the extracted vectors and the test vectors, thereby determining suitable best matches while avoiding the necessity to search the full database.
    Type: Application
    Filed: December 9, 2014
    Publication date: July 2, 2015
    Applicant: INTEL CORPORATION
    Inventor: Niraj Gupta
  • Patent number: 9042652
    Abstract: An apparatus may include a memory, a processor circuit, and a connected component labeling module. The connected component labeling module may be operative of the processor circuit to determine one or more connected components during reading of an image comprising a multiplicity of pixels from the memory, assign a label to a plurality of pixels of the multiplicity of pixels, generate one or more label connections for a respective one or more labels, each label connection linking a higher label to a lowest label for the same connected component, and write to the memory for each label of the one or more labels a lowest label as defined by the label connection for the each label after a label is assigned to each pixel.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: May 26, 2015
    Assignee: INTEL CORPORATION
    Inventors: Niraj Gupta, Oren Agam, Benny Eitan, Mostafa Hagog
  • Publication number: 20150135211
    Abstract: A computer implemented method and apparatus for improving viewer engagement in video advertising. The method comprises configuring a plurality of skip options for presentation in advertising content, such that each skip option of the plurality of skip options is presented in series for a limited duration during display of the advertising content until a presented one of the skip options is selected.
    Type: Application
    Filed: November 12, 2013
    Publication date: May 14, 2015
    Applicant: ADOBE SYSTEMS INCORPORATED
    Inventors: Naresh Chand Gupta, Anuj Jain, Niraj Gupta
  • Publication number: 20150125085
    Abstract: Techniques related to integral image coding are described herein.
    Type: Application
    Filed: November 4, 2013
    Publication date: May 7, 2015
    Inventor: Niraj Gupta
  • Publication number: 20150100414
    Abstract: A computer implemented method and apparatus for determining brand awareness before dismissing a video advertisement. The method comprises receiving video content, advertising content, and a test question, wherein the test question tests brand awareness of a viewer of the advertising content; playing the advertising content; presenting the test question; stopping the advertising content when an input is received that correctly answers the test question; and playing the video content.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Applicant: Adobe Systems Incorporated
    Inventor: Niraj Gupta
  • Publication number: 20150077422
    Abstract: Flood-fill techniques and architecture are disclosed. In accordance with one embodiment, the architecture comprises a hardware primitive with a software interface which collectively allow for both data-based and task-based parallelism in executing a flood-fill process. The hardware primitive is defined to do the flood-fill function and is scalable and may be implemented with a bitwise definition that can be tuned to meet power/performance targets, in some embodiments. In executing a flood-fill operation, and in accordance with an example embodiment, the software interface produces parallel threads and issues them to processing elements, such that each of the threads can run independently until done. Each processing element in turn accesses a flood-fill hardware primitive, each of which is configured to flood a seed inside an N×M image block. In some cases, processing element commands to the flood-fill hardware primitive(s) can be queued and acted upon pursuant to an arbitration scheme.
    Type: Application
    Filed: November 21, 2014
    Publication date: March 19, 2015
    Applicant: INTEL CORPORATION
    Inventors: Alon Gluska, Niraj Gupta, Mostafa Hagog, Dror Reif
  • Publication number: 20140379993
    Abstract: Methods and systems may provide for receiving, at a graphics processor, a workload from a host processor and using a kernel on the graphics processor to issue a thread group for execution of the workload on the graphics processor. Additionally, one or more coherency messages may be initiated, by the graphics processor, in response to a thread-related condition of one or more caches on the graphics processor. In one example, the thread-related condition is associated with the execution of the workload on the graphics processor and indicates that the one or more caches on the graphics processor are not coherent with a system memory associated with the host processor.
    Type: Application
    Filed: June 25, 2013
    Publication date: December 25, 2014
    Inventors: Niraj Gupta, Hong Jiang
  • Publication number: 20140379774
    Abstract: The system has first, second, third, and fourth subsystems. Each subsystem has first and second multipliers coupled, respectively, to first and second adders. Each multiplier has two inputs. The first adder is coupled to a first output, a first accumulator, and a bit shifter. The bit shifter is coupled to a third adder. The third adder is coupled to a multiplexer. The multiplexer is coupled to a second output and a second accumulator. The second adder is coupled to the third adder and the multiplexer. The first outputs of the first and second subsystems are coupled directly to a fourth adder, the second outputs of the first and second subsystems are coupled directly to a fifth adder, the first outputs of the third and fourth subsystems are coupled directly to a sixth adder, and the second outputs of the third and fourth subsystems are coupled directly to a seventh adder.
    Type: Application
    Filed: June 21, 2013
    Publication date: December 25, 2014
    Inventors: Niraj Gupta, Karthik N
  • Patent number: 8902238
    Abstract: Flood-fill techniques and architecture are disclosed. In accordance with one embodiment, the architecture comprises a hardware primitive with a software interface which collectively allow for both data-based and task-based parallelism in executing a flood-fill process. The hardware primitive is defined to do the flood-fill function and is scalable and may be implemented with a bitwise definition that can be tuned to meet power/performance targets, in some embodiments. In executing a flood-fill operation, and in accordance with an example embodiment, the software interface produces parallel threads and issues them to processing elements, such that each of the threads can run independently until done. Each processing element in turn accesses a flood-fill hardware primitive, each of which is configured to flood a seed inside an N×M image block. In some cases, processing element commands to the flood-fill hardware primitive(s) can be queued and acted upon pursuant to an arbitration scheme.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: December 2, 2014
    Assignee: Intel Corporation
    Inventors: Alon Gluska, Niraj Gupta, Mostafa Hagog, Dror Reif
  • Publication number: 20140313243
    Abstract: Systems, apparatus, articles, and methods are described including operations to generate a weighted look-up-table based at least in part on individual pixel input values within an active block region and on a plurality of contrast compensation functions. A second level compensation may be performed for a center pixel block of the active region based at least in part on the weighted look-up-table.
    Type: Application
    Filed: December 21, 2012
    Publication date: October 23, 2014
    Inventors: Niraj Gupta, Supratim Pal, Mahesh B. Chappalli, Yi-Jen Chiu, Hong Jiang
  • Publication number: 20140222884
    Abstract: Systems, apparatus and methods are described related to optimizing fixed point divide.
    Type: Application
    Filed: February 5, 2013
    Publication date: August 7, 2014
    Inventor: Niraj Gupta
  • Publication number: 20140119657
    Abstract: An apparatus may include a memory, a processor circuit, and a connected component labeling module. The connected component labeling module may be operative of the processor circuit to determine one or more connected components during reading of an image comprising a multiplicity of pixels from the memory, assign a label to a plurality of pixels of the multiplicity of pixels, generate one or more label connections for a respective one or more labels, each label connection linking a higher label to a lowest label for the same connected component, and write to the memory for each label of the one or more labels a lowest label as defined by the label connection for the each label after a label is assigned to each pixel.
    Type: Application
    Filed: November 1, 2012
    Publication date: May 1, 2014
    Inventors: Niraj Gupta, Oren Agam, Benny Eitan, Mostafa Hagog
  • Publication number: 20140104285
    Abstract: Flood-fill techniques and architecture are disclosed. In accordance with one embodiment, the architecture comprises a hardware primitive with a software interface which collectively allow for both data-based and task-based parallelism in executing a flood-fill process. The hardware primitive is defined to do the flood-fill function and is scalable and may be implemented with a bitwise definition that can be tuned to meet power/performance targets, in some embodiments. In executing a flood-fill operation, and in accordance with an example embodiment, the software interface produces parallel threads and issues them to processing elements, such that each of the threads can run independently until done. Each processing element in turn accesses a flood-fill hardware primitive, each of which is configured to flood a seed inside an N×M image block. In some cases, processing element commands to the flood-fill hardware primitive(s) can be queued and acted upon pursuant to an arbitration scheme.
    Type: Application
    Filed: October 15, 2012
    Publication date: April 17, 2014
    Inventors: Alon Gluska, Niraj Gupta, Mostafa Hagog, Dror Reif