Abstract: A memory device and a system that implements a single symbol correction, double symbol detection (SSC-DSD+) error correction scheme are provided. The scheme is implemented by calculating four syndrome symbols in accordance with a Reed-Solomon (RS) codeword; determining three location bytes in accordance with three corresponding pairs of syndrome symbols in the four syndrome symbols; and generating an output based on a comparison of the three location bytes. The output may include: corrected data responsive to determining that the three location bytes match; an indication of a detected-and-corrected error (DCE) responsive to determining that two of the three location bytes match; or an indication of a detected-yet-uncorrected error (DUE) responsive to determining that none of the three location bytes match. A variant of the SSC-DSD+ decoder may be implemented using a carry-free subtraction operation to perform sanity checking.

Abstract: Memory, used by a computer to store data, is generally prone to faults, including permanent faults (i.e. relating to a lifetime of the memory hardware), and also transient faults (i.e. relating to some external cause) which are otherwise known as soft errors. Since soft errors can change the state of the data in the memory and thus cause errors in applications reading and processing the data, there is a desire to characterize the degree of vulnerability of the memory to soft errors. In particular, once the vulnerability for a particular memory to soft errors has been characterized, cost/reliability trade-offs can be determined, or soft error detection mechanisms (e.g. parity) may be selectively employed for the memory. In some cases, memory faults can be diagnosed by redundant execution and a diagnostic coverage may be determined.

Abstract: A memory device and a system that implements a single symbol correction, double symbol detection (SSC-DSD+) error correction scheme are provided. The scheme is implemented by calculating four syndrome symbols in accordance with a Reed-Solomon (RS) codeword; determining three location bytes in accordance with three corresponding pairs of syndrome symbols in the four syndrome symbols; and generating an output based on a comparison of the three location bytes. The output may include: corrected data responsive to determining that the three location bytes match; an indication of a detected-and-corrected error (DCE) responsive to determining that two of the three location bytes match; or an indication of a detected-yet-uncorrected error (DUE) responsive to determining that none of the three location bytes match. A variant of the SSC-DSD+ decoder may be implemented using a carry-free subtraction operation to perform sanity checking.

Abstract: In general, data is susceptible to errors caused by faults in hardware (i.e. permanent faults), such as faults in the functioning of memory and/or communication channels. To detect errors in data caused by hardware faults, the error correcting code (ECC) was introduced, which essentially provides a sort of redundancy to the data that can be used to validate that the data is free from errors caused by hardware faults. In some cases, the ECC can also be used to correct errors in the data caused by hardware faults. However, the ECC itself is also susceptible to errors, including specifically errors caused by faults in the ECC logic. A method, computer readable medium, and system are thus provided for securing against errors in an ECC.

Abstract: Memory, used by a computer to store data, is generally prone to faults, including permanent faults (i.e. relating to a lifetime of the memory hardware), and also transient faults (i.e. relating to some external cause) which are otherwise known as soft errors. Since soft errors can change the state of the data in the memory and thus cause errors in applications reading and processing the data, there is a desire to characterize the degree of vulnerability of the memory to soft errors. In particular, once the vulnerability for a particular memory to soft errors has been characterized, cost/reliability trade-offs can be determined, or soft error detection mechanisms (e.g. parity) may be selectively employed for the memory. In some cases, memory faults can be diagnosed by redundant execution and a diagnostic coverage may be determined.

Abstract: Memory, used by a computer to store data, is generally prone to faults, including permanent faults (i.e. relating to a lifetime of the memory hardware), and also transient faults (i.e. relating to some external cause) which are otherwise known as soft errors. Since soft errors can change the state of the data in the memory and thus cause errors in applications reading and processing the data, there is a desire to characterize the degree of vulnerability of the memory to soft errors. In particular, once the vulnerability for a particular memory to soft errors has been characterized, cost/reliability trade-offs can be determined, or soft error detection mechanisms (e.g. parity) may be selectively employed for the memory. In some cases, memory faults can be diagnosed by redundant execution and a diagnostic coverage may be determined.

Abstract: In general, data is susceptible to errors caused by faults in hardware (i.e. permanent faults), such as faults in the functioning of memory and/or communication channels. To detect errors in data caused by hardware faults, the error correcting code (ECC) was introduced, which essentially provides a sort of redundancy to the data that can be used to validate that the data is free from errors caused by hardware faults. In some cases, the ECC can also be used to correct errors in the data caused by hardware faults. However, the ECC itself is also susceptible to errors, including specifically errors caused by faults in the ECC logic. A method, computer readable medium, and system are thus provided for securing against errors in an ECC.

Abstract: In general, data is susceptible to errors caused by faults in hardware (i.e. permanent faults), such as faults in the functioning of memory and/or communication channels. To detect errors in data caused by hardware faults, the error correcting code (ECC) was introduced, which essentially provides a sort of redundancy to the data that can be used to validate that the data is free from errors caused by hardware faults. In some cases, the ECC can also be used to correct errors in the data caused by hardware faults. However, the ECC itself is also susceptible to errors, including specifically errors caused by faults in the ECC logic. A method, computer readable medium, and system are thus provided for securing against errors in an ECC.

Abstract: Memory, used by a computer to store data, is generally prone to faults, including permanent faults (i.e. relating to a lifetime of the memory hardware), and also transient faults (i.e. relating to some external cause) which are otherwise known as soft errors. Since soft errors can change the state of the data in the memory and thus cause errors in applications reading and processing the data, there is a desire to characterize the degree of vulnerability of the memory to soft errors. In particular, once the vulnerability for a particular memory to soft errors has been characterized, cost/reliability trade-offs can be determined, or soft error detection mechanisms (e.g. parity) may be selectively employed for the memory. In some cases, memory faults can be diagnosed by redundant execution and a diagnostic coverage may be determined.

Abstract: Memory, used by a computer to store data, is generally prone to faults, including permanent faults (i.e. relating to a lifetime of the memory hardware), and also transient faults (i.e. relating to some external cause) which are otherwise known as soft errors. Since soft errors can change the state of the data in the memory and thus cause errors in applications reading and processing the data, there is a desire to characterize the degree of vulnerability of the memory to soft errors. In particular, once the vulnerability for a particular memory to soft errors has been characterized, cost/reliability trade-offs can be determined, or soft error detection mechanisms (e.g. parity) may be selectively employed for the memory. A method, computer readable medium, and system are provided for using liveness as a factor to evaluate memory vulnerability to soft errors.

Abstract: In general, data is susceptible to errors caused by faults in hardware (i.e. permanent faults), such as faults in the functioning of memory and/or communication channels. To detect errors in data caused by hardware faults, the error correcting code (ECC) was introduced, which essentially provides a sort of redundancy to the data that can be used to validate that the data is free from errors caused by hardware faults. In some cases, the ECC can also be used to correct errors in the data caused by hardware faults. However, the ECC itself is also susceptible to errors, including specifically errors caused by faults in the ECC logic. A method, computer readable medium, and system are thus provided for securing against errors in an ECC.

Abstract: Memory, used by a computer to store data, is generally prone to faults, including permanent faults (i.e. relating to a lifetime of the memory hardware), and also transient faults (i.e. relating to some external cause) which are otherwise known as soft errors. Since soft errors can change the state of the data in the memory and thus cause errors in applications reading and processing the data, there is a desire to characterize the degree of vulnerability of the memory to soft errors. In particular, once the vulnerability for a particular memory to soft errors has been characterized, cost/reliability trade-offs can be determined, or soft error detection mechanisms (e.g. parity) may be selectively employed for the memory. A method, computer readable medium, and system are provided for using liveness as a factor to evaluate memory vulnerability to soft errors.

Abstract: A method for a prediction correlation between a first group of branch instructions in a bunch of instructions and a second group of branch instructions in a bunch of instructions is disclosed. The method includes indicating a direction of a plurality of branch instructions in a bunch of instructions. More particularly, the method includes building an address composed of an instruction fetch address and bits in a history register. The method accesses a bunch of instructions using the fetch address and accesses a prediction bits set from a branch history table using the composed address. The accessed bunch of instructions are processed. Further, the history register and the branch history table are updated to correlate a first group of a branch instructions in the accessed bunch of instructions to a second group of branch instructions in a next group of branch instructions in the bunch of instructions.

Abstract: A method for a prediction correlation between a first group of branch instructions in a bunch of instructions and a second group of branch instructions in a bunch of instructions is disclosed. The method includes indicating a direction of a plurality of branch instructions in a bunch of instructions. More particularly, the method includes building an address composed of an instruction fetch address and bits in a history register. The method accesses a bunch of instructions using the fetch address and accesses a prediction bits set from a branch history table using the composed address. The accessed bunch of instructions are processed. Further, the history register and the branch history table are updated to correlate a first group of a branch instructions in the accessed bunch of instructions to a second group of branch instructions in a next group of branch instructions in the bunch of instructions.

Abstract: An apparatus generates patterns useful for testing storage devices using a modified form of a shift register. A control input and two bits are added and the least significant bit of the result is substituted in place of one of the bits which are rotatably shifted to generate subsequent patterns. The patterns generated may be used to test storage devices by writing the pattern to the storage device, reading the device and comparing the pattern read with the pattern written. A difference indicates a storage device error.

Abstract: An LCD controller for use e.g. in a portable computer provides gray scale shading for both monochromatic and color displays using frame rate control modulation for intensity shading for each pixel. The gray scale shading process and circuit do not require any memory for storing phase tiling matrices or frame modulation pattern sequences; both of these instead are generated in real time using a linear matrix logic structure. Use of linear matrix operations also allows generation of various phase shifts of frame modulation pattern sequences to provide a better image on the display. In addition to providing programmable 4, 8, or 16 intensity levels, the present method and apparatus provide that vertically, horizontally or diagonally adjacent pixels on the display never have the same phase in the same frame, and in addition that the pixel display drivers are uniformly loaded.

Abstract: Methods and apparati predict whether conditional branch computer instructions should be taken or not taken. A history register is maintained to record the history of groups of instructions, updated only once for each group. The history register and an address of one of the bytes of one of the instructions in each group are appended or otherwise combined to create an address to a table of two-bit saturating counters. The value of one of the bits of the counter at the address created is used for predicting all the conditional branch instructions for each branch in the group.

Abstract: Methods and apparati allow a more compact error correction code which corrects and detects one or more bit errors and detects a memory chip failure to be used for the detection and correction of errors. Rather than store data in groups of bits equal to the width of the memory chip, data is stored in groups of bits smaller than the width of a chip. An error correction code is used that detects the failure of a chip having the width of the group. Because the group is smaller than the width of the chip, a smaller error code may be used.

Abstract: A method and apparatus detects whether more than one object has been selected from a set of objects. A unique code and an error code is coupled to objects in the set. At least one object is selected and the unique codes from the selected object are logically summed, as are the error codes from the selected objects. A test code is generated from the logically summed unique code and tested for equality with the logically summed error code to determine if more than one object was selected.