Patents by Inventor Nitin Deshpande

Nitin Deshpande has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170301625
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 28, 2017
    Publication date: October 19, 2017
    Inventors: Ravindranath V. Mahajan, Christopher J. Nelson, Omkar G. Karhade, Feras Eid, Nitin A. Deshpande, Shawna M. Liff
  • Patent number: 9795038
    Abstract: Some example forms relate to an electronic package. The electronic package includes an electronic component and a substrate that includes a front side and a back side. The electronic component is mounted on the front side of the substrate and conductors are mounted on the back side of the substrate. The substrate is warped due to differences in the coefficients of thermal expansion between the electronic component and the substrate. An adhesive is positioned between the conductors on the back side of the substrate and an adhesive film is attached to the adhesive positioned between the conductors on the back side of the substrate.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Omkar Karhade, Nitin Deshpande, Nachiket Raravikar
  • Publication number: 20170290155
    Abstract: Embodiments of the present disclosure are directed towards electro-magnetic interference (EMI) shielding techniques and configurations. In one embodiment, an apparatus includes a first substrate, a die having interconnect structures coupled with the first substrate to route input/output (I/O) signals between the die and the first substrate and a second substrate coupled with the first substrate, wherein the die is disposed between the first substrate and the second substrate and at least one of the first substrate and the second substrate include traces configured to provide electro-magnetic interference (EMI) shielding for the die. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 20, 2017
    Publication date: October 5, 2017
    Inventors: Adel A. Elsherbini, Ravindranath Mahajan, John S. Guzek, Nitin A. Deshpande
  • Patent number: 9754890
    Abstract: A microelectronic structure includes a substrate having a first surface and a cavity extending into the substrate from the substrate first surface, a first microelectronic device and a second microelectronic device attached to the substrate first surface, and a bridge disposed within the substrate cavity and attached to the first microelectronic device and to the second microelectronic device. The bridge includes a plurality conductive vias extending from a first surface to an opposing second surface of the bridge, wherein the conductive vias are electrically coupled to deliver electrical signals from the substrate to the first microelectronic device and the second microelectronic device. The bridge further creates at least one electrical signal connection between the first microelectronic device and the second microelectronic device.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: September 5, 2017
    Assignee: Intel Corporation
    Inventors: Nitin A. Deshpande, Omkar G. Karhade
  • Patent number: 9741692
    Abstract: Methods of fabricating a microelectronic device comprising forming a microelectronic substrate having a plurality microelectronic device attachment bond pads and at least one interconnection bond pad formed in and/or on an active surface thereof, attaching a microelectronic device to the plurality of microelectronic device attachment bond pads, forming a mold chase having a mold body and at least one projection extending from the mold body, wherein the at least one projection includes at least one sidewall and a contact surface, contacting the mold chase projection contact surface to a respective microelectronic substrate interconnection bond pad, disposing a mold material between the microelectronic substrate and the mold chase, and removing the mold chase to form at least one interconnection via extending from a top surface of the mold material to a respective microelectronic substrate interconnection bond pad.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: August 22, 2017
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Nitin A. Deshpande, Edvin Cetegen, Eric J. Li, Debendra Mallik, Bassam M. Ziadeh
  • Patent number: 9716067
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: July 25, 2017
    Assignee: Intel Corporation
    Inventors: Ravindranath V. Mahajan, Christopher J. Nelson, Omkar G. Karhade, Feras Eid, Nitin A. Deshpande, Shawna M. Liff
  • Patent number: 9713255
    Abstract: Embodiments of the present disclosure are directed towards electro-magnetic interference (EMI) shielding techniques and configurations. In one embodiment, an apparatus includes a first substrate, a die having interconnect structures coupled with the first substrate to route input/output (I/O) signals between the die and the first substrate and a second substrate coupled with the first substrate, wherein the die is disposed between the first substrate and the second substrate and at least one of the first substrate and the second substrate include traces configured to provide electro-magnetic interference (EMI) shielding for the die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: July 18, 2017
    Assignee: INTEL CORPORATION
    Inventors: Adel A. Elsherbini, Ravindranath Mahajan, John S. Guzek, Nitin A. Deshpande
  • Publication number: 20170200621
    Abstract: Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top surface of the die. In an embodiment, the solder paste comprises a high-melting point metal, a solder matrix, intermetallic compounds and a polymer. The overmold layer has a high elastic modulus, a coefficient of thermal expansion similar to the substrate, and reduces the warpage of the package. In an embodiment, interconnects of a semiconductor package are formed with a no-slump solder paste that includes vents. Vents may be formed through a conductive network formed by the high-melting point metal, solder matrix and intermetallic compounds. In an embodiment, vents provide a path through the interconnect that allows for moisture outgassing. In an embodiment, a mold layer may be mechanically anchored to the interconnects by the vents, thereby providing improved mechanical continuity to the mold layer.
    Type: Application
    Filed: March 24, 2017
    Publication date: July 13, 2017
    Inventors: Omkar G. KARHADE, Nitin A. DESHPANDE, JR., Aditya Sundoctor VAIDYA, Nachiket R. RARAVIKAR, Eric J. LI
  • Patent number: 9685421
    Abstract: The subject matter of the present description relates to methods for the precise integration of microelectronic dice within a multichip package which substantially reduce or eliminate any misalign caused by the movement of the microelectronic dice during the integration process. These methods may include the use of a temporary adhesive in conjunction with a carrier having at least one recess for microelectronic die alignment, the use of a precision molded carrier for microelectronic die alignment, the use of magnetic alignment of microelectronic dice on a reusable carrier, and/or the use of a temporary adhesive with molding processes on a reusable carrier.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: June 20, 2017
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Ravindranath V Mahajan, Omkar Karhade, Nitin Deshpande
  • Patent number: 9685388
    Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: June 20, 2017
    Assignee: Intel Corporation
    Inventors: Yoshihiro Tomita, Jiro Kubota, Omkar G. Karhade, Shawna M. Liff, Kinya Ichikawa, Nitin A. Deshpande
  • Patent number: 9659899
    Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventors: Sandeep B. Sane, Shankar Ganapathysubramanian, Jorge Sanchez, Leonel R. Arana, Eric J. Li, Nitin A. Deshpande, Jiraporn Seangatith, Poh Chieh Benny Poon
  • Patent number: 9607964
    Abstract: Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top surface of the die. In an embodiment, the solder paste comprises a high-melting point metal, a solder matrix, intermetallic compounds and a polymer. The overmold layer has a high elastic modulus, a coefficient of thermal expansion similar to the substrate, and reduces the warpage of the package. In an embodiment, interconnects of a semiconductor package are formed with a no-slump solder paste that includes vents. Vents may be formed through a conductive network formed by the high-melting point metal, solder matrix and intermetallic compounds. In an embodiment, vents provide a path through the interconnect that allows for moisture outgassing. In an embodiment, a mold layer may be mechanically anchored to the interconnects by the vents, thereby providing improved mechanical continuity to the mold layer.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: March 28, 2017
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Nitin A. Deshpande, Jr., Aditya Sundoctor Vaidya, Nachiket R. Raravikar, Eric J. Li
  • Patent number: 9583470
    Abstract: An electronic device including a solder pad structure and methods of forming an electrical interconnection are shown. Solder pads including one or more projections extending from the pads are shown where the projections occupy only a fraction of a surface area of the pads. Processes such as thermal compression bonding using solder pads as described are also shown.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: February 28, 2017
    Assignee: Intel Corporation
    Inventors: Omkar Karhade, Nitin Deshpande
  • Patent number: 9576942
    Abstract: An integrated circuit assembly that includes a substrate; a member formed on the substrate; a first die mounted to the substrate within an opening in the member such that there is space between the first die and the member and the member surrounds the first die, and wherein the first die does not extend above an upper surface of the member; an underfill between the first the die and the substrate, wherein the underfill at least partially fills the space between the die and member; and a second die mounted to the first die and the member, wherein the second die is mounted to the member on all sides of the opening.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 21, 2017
    Assignee: Intel Corporation
    Inventors: Omkar Karhade, Nitin Deshpande, Bassam M. Ziadeh, Yoshihiro Tomita
  • Publication number: 20170040238
    Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.
    Type: Application
    Filed: October 18, 2016
    Publication date: February 9, 2017
    Applicant: Intel Corporation
    Inventors: Yoshihiro Tomita, Jiro Kubota, Omkar G. Karhade, Shawna M. Liff, Kinya Ichikawa, Nitin A. Deshpande
  • Publication number: 20160343666
    Abstract: A microelectronic structure includes a substrate having a first surface and a cavity extending into the substrate from the substrate first surface, a first microelectronic device and a second microelectronic device attached to the substrate first surface, and a bridge disposed within the substrate cavity and attached to the first microelectronic device and to the second microelectronic device. The bridge includes a plurality conductive vias extending from a first surface to an opposing second surface of the bridge, wherein the conductive vias are electrically coupled to deliver electrical signals from the substrate to the first microelectronic device and the second microelectronic device. The bridge further creates at least one electrical signal connection between the first microelectronic device and the second microelectronic device.
    Type: Application
    Filed: February 26, 2014
    Publication date: November 24, 2016
    Applicant: INTEL CORPORATION
    Inventors: Nitin A. Deshpande, Omkar G. Karhade
  • Patent number: 9502368
    Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: November 22, 2016
    Assignee: Intel Corporation
    Inventors: Yoshihiro Tomita, Jiro Kubota, Omkar G. Karhade, Shawna M. Liff, Kinya Ichikawa, Nitin A. Deshpande
  • Publication number: 20160300824
    Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction.
    Type: Application
    Filed: June 15, 2016
    Publication date: October 13, 2016
    Applicant: Intel Corporation
    Inventors: Omkar G. Karhade, John S. Guzek, Johanna M. Swan, Christopher J. Nelson, Nitin A. Deshpande, William J. Lambert, Charles A. Gealer, Feras Eid, Islam A. Salama, Kemal Aygun, Sasha N. Oster, Tyler N. Osborn
  • Publication number: 20160268231
    Abstract: Methods of fabricating a microelectronic device comprising forming a microelectronic substrate having a plurality microelectronic device attachment bond pads and at least one interconnection bond pad formed in and/or on an active surface thereof, attaching a microelectronic device to the plurality of microelectronic device attachment bond pads, forming a mold chase having a mold body and at least one projection extending from the mold body, wherein the at least one projection includes at least one sidewall and a contact surface, contacting the mold chase projection contact surface to a respective microelectronic substrate interconnection bond pad, disposing a mold material between the microelectronic substrate and the mold chase, and removing the mold chase to form at least one interconnection via extending from a top surface of the mold material to a respective microelectronic substrate interconnection bond pad.
    Type: Application
    Filed: September 15, 2014
    Publication date: September 15, 2016
    Applicant: INTEL CORPORATION
    Inventors: Omkar G. Karhade, Nitin A. Deshpande, Edvin Cetegen, Eric J. Li, Debendra Mallik, Bassam M. Ziadeh
  • Publication number: 20160260688
    Abstract: An electronic assembly that includes a first electronic device. The first electronic device includes a cavity that extends into a back side of the first electronic device. The electronic assembly further includes a second electronic device. The second electronic device is mounted to the first electronic device within the cavity in the first electronic device. In some example forms of the electronic assembly, the first electronic device and the second electronic device are each a die. It should be noted that other forms of the electronic assembly are contemplated where only one of the first electronic device and the second electronic device is a die. In some forms of the electronic assembly, the second electronic device is soldered to the first electronic device.
    Type: Application
    Filed: July 2, 2014
    Publication date: September 8, 2016
    Inventors: Nitin Deshpande, Ravi V. Mahajan