Patents by Inventor Noémie Blanc

Noémie Blanc has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11121042
    Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with silicon nitride. The silicon nitride situated above the first region is doped by ion implantation. Trenches are etched through the silicon nitride and the doped silicon nitride is partially etching in an isotropic manner. The trenches are filled with an insulator to a level situated above that of the first region. The silicon nitride is removed resulting in the edges of the first region only being covered with an insulator annulus.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: September 14, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Franck Julien, Frédéric Chairat, Noémie Blanc, Emmanuel Blot, Philippe Roux, Gerald Theret
  • Publication number: 20200152523
    Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with silicon nitride. The silicon nitride situated above the first region is doped by ion implantation. Trenches are etched through the silicon nitride and the doped silicon nitride is partially etching in an isotropic manner. The trenches are filled with an insulator to a level situated above that of the first region. The silicon nitride is removed resulting in the edges of the first region only being covered with an insulator annulus.
    Type: Application
    Filed: January 10, 2020
    Publication date: May 14, 2020
    Inventors: Franck Julien, Frédéric Chairat, Noémie Blanc, Emmanuel Blot, Philippe Roux, Gerald Theret
  • Patent number: 10553499
    Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with silicon nitride. The silicon nitride situated above the first region is doped by ion implantation. Trenches are etched through the silicon nitride and the doped silicon nitride is partially etching in an isotropic manner. The trenches are filled with an insulator to a level situated above that of the first region. The silicon nitride is removed resulting in the edges of the first region only being covered with an insulator annulus.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: February 4, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Franck Julien, Frédéric Chairat, Noémie Blanc, Emmanuel Blot, Philippe Roux, Gerald Theret
  • Publication number: 20180358270
    Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with silicon nitride. The silicon nitride situated above the first region is doped by ion implantation. Trenches are etched through the silicon nitride and the doped silicon nitride is partially etching in an isotropic manner. The trenches are filled with an insulator to a level situated above that of the first region. The silicon nitride is removed resulting in the edges of the first region only being covered with an insulator annulus.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 13, 2018
    Inventors: Franck Julien, Frédéric Chairat, Noémie Blanc, Emmanuel Blot, Philippe Roux, Gerald Theret