Patents by Inventor Noboru Horie

Noboru Horie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210111389
    Abstract: A predoping method for a negative electrode active material to dope the negative electrode active material with lithium ions using an electrolyte solution that includes lithium ions. The electrolyte solution includes at least one type of additive having a reduction potential higher than a reduction potential of a solvent contained in the electrolyte solution.
    Type: Application
    Filed: February 21, 2019
    Publication date: April 15, 2021
    Applicants: NISSAN MOTOR CO., LTD., JSR Corporation
    Inventors: Shotaro DOI, Yuki KUSACHI, Noboru YAMAUCHI, Tomohiro KABURAGI, Hideaki HORIE, Yusuke NAKASHIMA, Kazuya TSUCHIDA, Naofumi SHOJI, Koji SUMIYA, Shigehito ASANO, Yasuyuki KOGA, Nobuo ANDO, Terukazu KOKUBO
  • Publication number: 20200395594
    Abstract: A predoping method for a negative electrode active material to dope the negative electrode active material with lithium ions. The predoping method for a negative electrode active material includes: a predoping process and a post-doping modification process. In the predoping process, the negative electrode active material is doped with lithium ions, to thereby reduce a potential of the negative electrode active material relative to lithium metal. In the post-doping modification process, after the predoping process, reaction is caused between a reactive compound that is reactive with lithium ions and lithium ions doped into the negative electrode active material, to thereby increase the potential of the negative electrode active material relative to lithium metal. The potential of the negative electrode active material relative to lithium metal is 0.8 V or more at completion of the post-doping modification process.
    Type: Application
    Filed: February 21, 2019
    Publication date: December 17, 2020
    Applicants: NISSAN MOTOR CO., LTD., JSR Corporation
    Inventors: Shotaro DOI, Yuki KUSACHI, Noboru YAMAUCHI, Tomohiro KABURAGI, Hideaki HORIE, Yusuke NAKASHIMA, Kazuya TSUCHIDA, Naofumi SHOJI, Koji SUMIYA, Shigehito ASANO, Yasuyuki KOGA, Nobuo ANDO, Terukazu KOKUBO
  • Patent number: 7274805
    Abstract: There is no surveillance camera system optimum for monitoring an important monitor place by a surveillance camera mainly for crime prevention day and night without humans in attendance, which can automatically monitor the place without humans in attendance and, when something suspicious is found, follow the suspicious without humans in attendance, and accurately monitor the suspicious at high precision. The present invention provides a surveillance camera driving method achieving such a system having the function of obtaining video image signals by two or more surveillance cameras each having a three-dimensional positioning pan tilt head function, organically processing the video information, comparing the processed information with input data of a plane picture or the like or data of pictures of a front view and a side view or the like, and determining whether the processed video signal is the same as the input data or not.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: September 25, 2007
    Assignee: Japan Servo Co., Ltd.
    Inventors: Noboru Horie, Masafumi Sakamoto
  • Publication number: 20040041909
    Abstract: There is no surveillance camera system optimum for monitoring an important monitor place by a surveillance camera mainly for crime prevention day and night without humans in attendance, which can automatically monitor the place without humans in attendance and, when something suspicious is found, follow the suspicious without humans in attendance, and accurately monitor the suspicious at high precision. The present invention provides a surveillance camera driving method achieving such a system having the function of obtaining video image signals by two or more surveillance cameras each having a three-dimensional positioning pan tilt head function, organically processing the video information, comparing the processed information with input data of a plane picture or the like or data of pictures of a front view and a side view or the like, and determining whether the processed video signal is the same as the input data or not.
    Type: Application
    Filed: August 29, 2003
    Publication date: March 4, 2004
    Applicant: JAPAN SERVO CO., LTD.
    Inventors: Noboru Horie, Masafumi Sakamoto
  • Patent number: 4942536
    Abstract: In a case where an electronic circuit having the same function is to be realized by a different device, it is indispensable to prepare circuit diagrams conforming to devices and to utilize them for the job of circuit simulation or chip layout. When the circuit diagrams are to be automatically translated for the above purpose, translation rules become different depending upon the connective relations of an element to be translated, with other elements in the circuit or upon a function performed by the element. The present invention puts the rules into knowledge from the viewpoint of knowledge engineering and utilizes it thereby to realize the intended purpose.
    Type: Grant
    Filed: April 21, 1986
    Date of Patent: July 17, 1990
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.
    Inventors: Toshinori Watanabe, Fumihiko Mori, Tamotsu Nishiyama, Makoto Furihata, Yasuo Kominami, Noboru Horie
  • Patent number: 4803636
    Abstract: In order to translate an original circuit consisting of a set of first devices into a target circuit which consists of a set of second devices different from the first devices, and which has the same functions as the original circuit, provision is made of memory means for storing translation rules in the first devices, translation rules in the second devices, and translation rules between the first devices and the second devices, and translation means which successively refers to these translation rules and translates the original circuit data into the target circuit data via steps that translate the original circuit data into a plurality of intermediate data.
    Type: Grant
    Filed: September 25, 1986
    Date of Patent: February 7, 1989
    Assignees: Hitachi Ltd., Hitachi Micro Computer Eng. Ltd.
    Inventors: Tamotsu Nishiyama, Toshinori Watanabe, Noboru Horie, Makoto Furihata, Yasuo Kominami, Fumihiko Mori
  • Patent number: 4651284
    Abstract: The structure of a circuit which is given basic net data is stored as a pattern, the compliance of the basic net data with the pattern is checked by the separately prepared search function, and upon fulfillment of compliance the pattern is determined to exist within the circuit. The subcircuit to be recognized by elements is not directly defined, but is defined using an intermediate expression defined recursively so as to implement a search through pattern matching. In another form, one input terminal is specified, which is followed by a search for blocks having the terminal as an input node and the search for blocks having one of the output node strings as an input node recursively and cyclically until the output terminal is reached, so as to extract a string of nodes on which the signal is propagated. The system is provided with functions for recognizing and comprehending subsidiary structures of the circuit which are not defined by the entered net data.
    Type: Grant
    Filed: July 26, 1985
    Date of Patent: March 17, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Toshinori Watanabe, Tetsuya Masuishi, Koji Sasaki, Koichi Haruna, Noboru Horie
  • Patent number: 4122481
    Abstract: A semiconductor IC structure including a plurality of isolated devices in a single substrate of a first conductivity type comprising at least three wells of a second conductivity type formed in the substrate, two of the wells reaching different edges of a buried layer of the second conductivity type at the bottom of the substrate to define a first zone of the first conductivity type in the substrate and the other wells defining at least one second zone of the first conductivity type in the substrate, and a method of fabricating a semiconductor IC structure of the above-mentioned type.
    Type: Grant
    Filed: June 22, 1977
    Date of Patent: October 24, 1978
    Assignee: Hitachi, Ltd.
    Inventor: Noboru Horie
  • Patent number: 4080616
    Abstract: A protective element for preventing electrostatic puncture of a semiconductor integrated circuit comprises a semiconductor substrate of one conductivity type, a first semiconductor region of the opposite conductivity type formed within a selected part of the surface of the semiconductor substrate, and a second semiconductor region of the one conductivity type formed within a selected part of the surface of the first semiconductor region, the first and second semiconductor regions being partially short-circuited. When a surge pulse voltage is impressed between the substrate and the second region, the element operates as a diode or a transistor so as to absorb the surge pulse.
    Type: Grant
    Filed: February 28, 1974
    Date of Patent: March 21, 1978
    Assignee: Hitachi, Ltd.
    Inventor: Noboru Horie
  • Patent number: 4051506
    Abstract: A semiconductor device comprising at least a pair of NPN and PNP transistors is improved. This semiconductor device is characterized in that at least one pair of vertical transistors are formed in a semiconductor layer of the second conductivity type formed on a semiconductor substrate of the first conductivity type, the semiconductor layer of the second conductivity type serving as both the collector of one of the transistors and the base of the other and that the transistors are electrically insulated from each other by organic insulator formed on the inorganic insulating film on the semiconductor substrate. Thus, a semiconductor device can be obtained in which PNP transistors having good characteristics such as current amplification factor h.sub.FE and gain-bandwidth product f.sub.T are incorporated in an integrated circuit consisting mainly of NPN transistors.
    Type: Grant
    Filed: May 25, 1976
    Date of Patent: September 27, 1977
    Assignee: Hitachi, Ltd.
    Inventor: Noboru Horie
  • Patent number: 4049476
    Abstract: A method of manufacturing a semiconductor integrated circuit device, which includes at least one junction field-effect transistor and at least one bipolar transistor, is characterized in that a groove portion is formed by chemically etching a part of a diffused layer for the channel region of the junction field-effect transistor, and that a layer for the gate of the junction field-effect transistor having a conductivity type to opposite to that of the channel region is formed by diffusion in the diffused layer of the channel region beneath the groove portion, whereby the pinch-off voltage V.sub.p of the junction field-effect transistor is made as small as possible and is also made smaller than the base-emitter reverse withstand voltage V.sub.BEO of the bipolar transistor.
    Type: Grant
    Filed: September 29, 1975
    Date of Patent: September 20, 1977
    Assignee: Hitachi, Ltd.
    Inventor: Noboru Horie
  • Patent number: 4030954
    Abstract: A method of manufacturing a semiconductor integrated circuit device including N-P-N transistors is characterized in that a base region of at least one of the N-P-N transistors is partially etched and removed with chemicals, thus to be formed with a depression, and that an emitter region opposite in the conductivity type to the base region is formed in the base region beneath the depression, whereby the at least one N-P-N transistor is made higher in the current gain h.sub.FE than the other N-P-N transistors being the main constituents of the integrated circuit device.
    Type: Grant
    Filed: September 30, 1975
    Date of Patent: June 21, 1977
    Assignee: Hitachi, Ltd.
    Inventor: Noboru Horie
  • Patent number: 4025802
    Abstract: In a capacitance circuit having a capacitance element which exhibits a breakdown characteristic and which generates noises at breakdown, the improvement comprising a constant-voltage element, which has a lower breakdown voltage than the capacitance element and a lower noise level than the capacitance element in the state of breakdown, connected in parallel with the capacitance element. The voltage across the capacitance element is clamped at the breakdown voltage of the constant-voltage element, so that the capacitance element is prevented from breaking down and thus generating noise components.
    Type: Grant
    Filed: July 17, 1975
    Date of Patent: May 24, 1977
    Assignee: Hitachi, Ltd.
    Inventors: Fumihito Inoue, Yoshiji Nakajima, Noboru Horie
  • Patent number: 3969748
    Abstract: A multiple transistor consists of vertical and lateral transistors, the collector region of the lateral transistor is formed by diffusion within the diffused base region of the vertical transistor simultaneously with the emitter region of the vertical transistor, into a structure in which the base of the vertical transistor and the collector of the lateral transistor are short-circuited. As a result the current gain of the lateral transistor can be varied by changing the area of the collector region.
    Type: Grant
    Filed: May 31, 1974
    Date of Patent: July 13, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Noboru Horie, Kazuo Hoya
  • Patent number: 3962718
    Abstract: In a capacitance circuit having a capacitance element which exhibits a breakdown characteristic and which generates noises at breakdown, the improvement comprising a constant-voltage element, which has a lower breakdown voltage than the capacitance element and a lower noise level than the capacitance element in the state of breakdown, connected in parallel with the capacitance element. The voltage across the capacitance element is clamped at the breakdown voltage of the constant-voltage element, so that the capacitance element is prevented from breaking down and thus generating noise components.
    Type: Grant
    Filed: October 4, 1973
    Date of Patent: June 8, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Fumihito Inoue, Yoshiji Nakajima, Noboru Horie