Abstract: A clock data recovery circuit includes a circuit that receives a data signal for which each of a plurality of potential levels is associated with a value of 2 bits or more, based on a result of a first comparison that compares the 3 or more first thresholds with the data signal at timing synchronized with a clock signal; a circuit that outputs a result of a second comparison that compares the data signal with a second threshold at the timing; a circuit that generates a phase difference signal indicating whether to advance or delay a phase of the clock signal, based on the result of the determination and the result of the second comparison; a filter that generates a phase adjusted value indicating an adjustment amount of the phase, based on the phase difference signal; and a circuit that adjusts the phase based on the phase adjusted value.

Abstract: A clock data recovery circuit includes a circuit that receives a data signal for which each of a plurality of potential levels is associated with a value of 2 bits or more, based on a result of a first comparison that compares the 3 or more first thresholds with the data signal at timing synchronized with a clock signal; a circuit that outputs a result of a second comparison that compares the data signal with a second threshold at the timing; a circuit that generates a phase difference signal indicating whether to advance or delay a phase of the clock signal, based on the result of the determination and the result of the second comparison; a filter that generates a phase adjusted value indicating an adjustment amount of the phase, based on the phase difference signal; and a circuit that adjusts the phase based on the phase adjusted value.

Abstract: A micro electro mechanical systems (MEMS) control circuit includes a memory and a processor coupled to the memory and the processor configured to obtain an amplitude mean value of a monitor signal representing an amplitude in a direction of a horizontal axis of an MEMS device every unit time, compare the amplitude mean value with a reference value, and change a driving frequency of the MEMS device in a case where identical comparison results last consecutively a predetermined number of times.

Abstract: A drive circuit for supplying a drive current to light emitting elements includes an output circuit that sets a magnitude of the drive current based on an assumed value of a threshold current being a threshold value of the drive current, an acquisition circuit that acquires an optical-output monitor value indicating a magnitude of an optical output of the light emitting elements, a first calculation circuit that calculates an average value of the drive current in a predetermined period in a frame period as an average drive current value for each of the predetermined period, a second calculation circuit that calculates an average value of the optical-output monitor values in the predetermined period as an average optical-output monitor value, and an adjustment circuit that adjusts the assumed value of the threshold current value based on the average drive current value and the average optical-output monitor value.

Abstract: A drive circuit for supplying a drive current to light emitting elements includes an output circuit that sets a magnitude of the drive current based on an assumed value of a threshold current being a threshold value of the drive current, an acquisition circuit that acquires an optical-output monitor value indicating a magnitude of an optical output of the light emitting elements, a first calculation circuit that calculates an average value of the drive current in a predetermined period in a frame period as an average drive current value for each of the predetermined period, a second calculation circuit that calculates an average value of the optical-output monitor values in the predetermined period as an average optical-output monitor value, and an adjustment circuit that adjusts the assumed value of the threshold current value based on the average drive current value and the average optical-output monitor value.

Abstract: A non-transitory computer-readable recording medium stores a state machine dividing program that causes a computer to execute a process including: determining whether a design value based on circuit information that indicates a circuit that controls a computation process by using a state machine is greater than a predetermined reference value; and dividing, when the design value is greater than the reference value, the state machine into a plurality of state machines.

Abstract: A frequency offset estimation circuit estimates a frequency offset that indicates a difference between a carrier frequency of a received optical signal and a frequency of a local oscillation light used to recover a transmission signal from the received optical signal. The frequency offset estimation circuit includes: a phase difference detector configured to detect a phase difference due to the frequency offset between a first symbol and a second symbol that is transmitted after the first symbol by a specified symbol interval based on a phase of the first symbol and a phase of the second symbol; an estimator configured to estimate the frequency offset based on the phase difference detected by the phase difference detector; and a symbol interval controller configured to specify the symbol interval based on the frequency offset estimated by the estimator.

Abstract: A non-transitory computer-readable recording medium stores a state machine dividing program that causes a computer to execute a process including: determining whether a design value based on circuit information that indicates a circuit that controls a computation process by using a state machine is greater than a predetermined reference value; and dividing, when the design value is greater than the reference value, the state machine into a plurality of state machines.

Abstract: A calculation method executed by a computer, the calculation method includes calculating, using a processor, a length of one side of a second module based on an area of the second module that is included in a first module in a circuit and includes devices; and calculating, using the processor, a length of a wiring of the first module based on the calculated length and the number of fan-outs of the first module.

Abstract: A frequency offset estimation circuit estimates a frequency offset that indicates a difference between a carrier frequency of a received optical signal and a frequency of a local oscillation light used to recover a transmission signal from the received optical signal. The frequency offset estimation circuit includes: a phase difference detector configured to detect a phase difference due to the frequency offset between a first symbol and a second symbol that is transmitted after the first symbol by a specified symbol interval based on a phase of the first symbol and a phase of the second symbol; an estimator configured to estimate the frequency offset based on the phase difference detected by the phase difference detector; and a symbol interval controller configured to specify the symbol interval based on the frequency offset estimated by the estimator.

Abstract: A wiring inspection apparatus includes a first calculating unit, a second calculating unit, and an output unit. The first calculating unit calculates the number of components arranged along two sides, one of which extends in a first direction and the other one of which extends in a second direction, of a minimum rectangle including a transmission component and a reception component. The second calculating unit calculates the number of the components arranged along the two sides at a predetermined arrangement density of relay components. When the number of the relay components is greater than the number of the components calculated by the second calculating unit, the output unit outputs information indicating the presence of a wiring extending in a direction opposite to a direction from the transmission component to the reception component among wirings connecting the transmission component, the reception component, and the relay components.

Abstract: A wiring inspection apparatus includes a dividing unit, a calculating unit, and an output unit. The dividing unit draws a boundary line in a predetermined area between a transmission component and a reception component, to divide the predetermined area into a first area containing the transmission component and a second area containing the reception component. The transmission component transmits a signal to the reception component via relay components. The calculating unit calculates a number of wirings that connect the components across the boundary line, based on positions of the transmission component, the reception component, and the relay components in the predetermined area. The output unit outputs information indicating the presence of a wiring extending in a direction opposite to a direction from the transmission component to the reception component, when the number of the wirings calculated by the calculating unit is equal to or greater than a predetermined value.

Abstract: A wiring inspection apparatus includes a first calculating unit, a second calculating unit, and an output unit. The first calculating unit calculates the number of components arranged along two sides, one of which extends in a first direction and the other one of which extends in a second direction, of a minimum rectangle including a transmission component and a reception component. The second calculating unit calculates the number of the components arranged along the two sides at a predetermined arrangement density of relay components. When the number of the relay components is greater than the number of the components calculated by the second calculating unit, the output unit outputs information indicating the presence of a wiring extending in a direction opposite to a direction from the transmission component to the reception component among wirings connecting the transmission component, the reception component, and the relay components.

Abstract: A wiring inspection apparatus includes a dividing unit, a calculating unit, and an output unit. The dividing unit draws a boundary line in a predetermined area between a transmission component and a reception component, to divide the predetermined area into a first area containing the transmission component and a second area containing the reception component. The transmission component transmits a signal to the reception component via relay components. The calculating unit calculates a number of wirings that connect the components across the boundary line, based on positions of the transmission component, the reception component, and the relay components in the predetermined area. The output unit outputs information indicating the presence of a wiring extending in a direction opposite to a direction from the transmission component to the reception component, when the number of the wirings calculated by the calculating unit is equal to or greater than a predetermined value.

Abstract: A calculation method executed by a computer, the calculation method includes calculating, using a processor, a length of one side of a second module based on an area of the second module that is included in a first module in a circuit and includes devices; and calculating, using the processor, a length of a wiring of the first module based on the calculated length and the number of fan-outs of the first module.

Abstract: There is provided a gateway apparatus that controls a forwarding process of frame data between multiple communication channels, said gateway apparatus including a search engine that is respectively provided for each of the multiple communication channels to route the frame data between the multiple communication channels, and a first storage portion that is respectively provided for each of the multiple communication channels to temporarily stores the frame data routed.

Abstract: A data transfer device for storing only transfer data for which updating is necessary in the storage unit of a transfer source, transferring the transfer data by a transfer control unit, temporarily storing the transfer data in a register provided in a transfer destination circuit, transferring the transfer data stored in the register to the discontinuous storage area of the transfer destination circuit according to the map information of a map register, and transferring data for which updating is necessary to the transfer destination circuit.

Abstract: There is provided a gateway apparatus that controls a forwarding process of frame data between multiple communication channels, said gateway apparatus including a search engine that is respectively provided for each of the multiple communication channels to route the frame data between the multiple communication channels, and a first storage portion that is respectively provided for each of the multiple communication channels to temporarily stores the frame data routed.