Abstract: A volume circuit contains resistive ladder circuits, from which a desired fractional voltage output (Vs) is extracted and supplied to an amplifier to provide an output voltage (Vout). The resistive ladder circuits comprise multiple lines of series resistances, wherein each line contains a resistance portion ‘nR’ (where ‘n’ denotes a division index, and ‘R’ denotes an element resistance) that is connected in parallel with a next line, so that an overall resistance of following lines is ‘(n?1)×n’ times larger than the element resistance. Secondary resistive ladder circuits can be additionally arranged in series in order to control a secondary amplifier that absorbs excessive currents flowing into the resistive ladder circuits. The secondary resistive ladder circuits are constituted symmetrically with the resistive ladder circuits, in which output terminals (t1-t12) are all set to the same potential.

Abstract: A triangular wave generating circuit adapted to a class-D amplifier is designed not to use a PLL circuit and to secure robustness regarding an amplification gain irrespective of variations of voltages, thus producing a high-quality triangular wave with a simple circuit constitution. First and second constant currents, which are generated in proportion to positive and negative voltages, are alternately and periodically selected using high impedance elements without causing noise. A first integrator produces a triangular wave in response to charged electricity realized by the first and second constant currents, wherein the triangular wave is supplied to a second integrator performing servo-amplification operation so as to suppress phase shifts thereof. Hence, it is possible to maintain a constant gain for the class-D amplifier irrespective of variations of voltages since the maximal and minimal voltages values of the triangular wave are made proportional to the positive and negative voltages.

Abstract: An image forming system includes: (1) an image forming apparatus and (2) a film package having a plurality of photosensitive sheet films and a light shielding bag that packs the plurality of photosensitive sheet films. Herein, the light shielding bag includes a bag section, a cut section to be cut at a first end portion of the bag section, and a holding section opposite the first end portion; after the cut section is cut, the film package is loaded on the loading section and mounted on the main body of the apparatus, the holding section is pulled from outside to take out the bag from the apparatus, and the photosensitive sheet films remain loaded on the loading section; and a length of the holding section outside the main body of the apparatus is smaller than or equal to 70 mm.

Abstract: A lateral PNP transistor PB and a lateral NPN transistor NB are serially connected between an input terminal and a reference potential (ground potential). In the transistor PB, a diode D1 is formed. In the transistor NB, a diode D3 is formed. When an ESD of +2000 V is input, the transistor NB turns on, whereas when an ESD of ?2000 V is input, the transistor PB turns on. The level of a positive signal capable of being input is limited by the inverse breakdown voltage (e.g., 18 to 50 V) of the diode D3, whereas the level of a negative signal capable of being input is limited by the inverse breakdown voltage (e.g., 13 to 15 V) of the diode D1.

Abstract: Several sheets of sheet-shaped photosensitive material 1 are stacked on a paper tray container 2 prepared by press-forming stencil paper sheet, the photosensitive material 1 stacked on said paper tray container is inserted into a moisture-proof and light-shielding bag 3 made of a photosensitive material packaging material having moisture-proof and light-shielding properties and having an aluminum thin foil layer, and the moisture-proof and light-shielding bag 3 is sealed tight under a reduced pressure vacuum.

Abstract: A pulse-width modulation (PWM) amplifier is adapted to a class-D amplifier in which an analog input signal is subjected to integration, pulse-width modulation, and switched amplification, wherein a glitch elimination circuit eliminates noise from a pulse-width modulated signal, from which a high pulse signal and a low pulse signal are isolated such that each pulse is delayed by a dead time at the leading-edge timing thereof. When both of them are simultaneously set to a high level, one of them is reduced in level. In response to the occurrence of clipping, an integration constant applied to an operational amplifier is automatically changed from a primary integration constant to a secondary integration constant. When the clipped state is sustained for a prescribed time, an inversion pulse is compulsorily introduced into the pulse-width modulated signal.

Abstract: A triangular wave generating circuit adapted to a class-D amplifier is designed not to use a PLL circuit and to secure robustness regarding an amplification gain irrespective of variations of voltages, thus producing a high-quality triangular wave with a simple circuit constitution. First and second constant currents, which are generated in proportion to positive and negative voltages, are alternately and periodically selected using high impedance elements without causing noise. A first integrator produces a triangular wave in response to charged electricity realized by the first and second constant currents, wherein the triangular wave is supplied to a second integrator performing servo-amplification operation so as to suppress phase shifts thereof. Hence, it is possible to maintain a constant gain for the class-D amplifier irrespective of variations of voltages since the maximal and minimal voltages values of the triangular wave are made proportional to the positive and negative voltages.

Abstract: An operational amplifier has a differential amplifier stage comprising a pair of first PMOS transistors for inputting signals, which are arranged between a positive voltage supply coupled with a first constant current source and a negative voltage supply, wherein second PMOS transistors of a high voltage resistant type, gates of which are biased to a prescribed voltage, are arranged on current paths lying between the first PMOS transistors and the negative voltage supply together with load resistors. Herein, each of drain voltages of the first PMOS transistors is limited to a certain value that is higher than the prescribed voltage by a gate threshold voltage. Therefore, even when the first PMOS transistors are configured of a normal voltage resistant type, it is possible to reliably prevent voltages applied to the first PMOS transistors from exceeding breakdown voltages thereof, thus avoiding unnecessary reduction of an S/N ratio.

Abstract: An input signal (SIN) is inverted by an inverter (101), and the inverted input signal is entered into a tri-state type inverter (104). An output portion of this inverter is connected via a delay path (105) to an input portion of an operational amplifier (106). This operational amplifier owns a hysteresis characteristic with respect to a signal entered thereinto. An exclusive-OR gate circuit (103) controls to set the output state of the inverter to a low impedance state upon receipt of a signal (S11) obtained by inverting the input signal, and controls to set the output state of the inverter to a high impedance state upon receipt of a signal (S16) output from the operational amplifier. As a result, an amplitude of a signal (S15) is limited to a constant amplitude in response to the hysteresis characteristic of the operational amplifier (106), and a delay time is made constant.

Abstract: An input protection circuit is provided which has a high electrostatic discharge (ESD) breakdown voltage and can input a signal in a wide positive and negative voltage range. In a surface layer of a substrate, a well and a field insulating film are formed. An emitter region is formed in the well to form a lateral bipolar transistor having the well as its base. Another emitter region is formed in the surface layer of the substrate to form another lateral bipolar transistor having the well as its collector. A gate electrode layer is formed on the field insulating film between the well and the other emitter region to form a MOS transistor. The emitter region is connected to an input terminal, the well is connected to the gate electrode layer, and the other emitter region and substrate are connected to a ground potential.

Abstract: A lateral PNP transistor PB and a lateral NPN transistor NB are serially connected between an input terminal and a reference potential (ground potential). In the transistor PB, a diode D1 is formed. In the transistor NB, a diode D3 is formed. When an ESD of +2000 V is input, the transistor NB turns on, whereas when an ESD of ?2000 V is input, the transistor PB turns on. The level of a positive signal capable of being input is limited by the inverse breakdown voltage (e.g., 18 to 50 V) of the diode D3, whereas the level of a negative signal capable of being input is limited by the inverse breakdown voltage (e.g., 13 to 15 V) of the diode D1.

Abstract: A lateral PNP transistor PB and a lateral NPN transistor NB are serially connected between an input terminal and a reference potential (ground potential). In the transistor PB, a diode D1 is formed. In the transistor NB, a diode D3 is formed. When an ESD of +2000 V is input, the transistor NB turns on, whereas when an ESD of ?2000 V is input, the transistor PB turns on. The level of a positive signal capable of being input is limited by the inverse breakdown voltage (e.g., 18 to 50 V) of the diode D3, whereas the level of a negative signal capable of being input is limited by the inverse breakdown voltage (e.g., 13 to 15 V) of the diode D1.

Abstract: A laser diode driving circuit is provided, which is capable of supplying a laser diode thereof with a high-speed pulse current. A current source supplies a current to the laser diode. An NMOS transistor as a first switch is connected between the current source and the laser diode. An NMOS transistor as a second switch is connected between a junction between the current source and the first switch and a pseudo load. A controller supplies a first voltage pulse signal to the first switch and a second voltage pulse signal opposite in phase to the first voltage pulse signal to the second switch to switch the first and second switches in a complementary manner.

Abstract: Optical disk writing apparatus includes a flexible substrate connecting a main sheep and a pickup section. Because the flexible substrate has poor frequency characteristics, a frequency band for signals transmitted through the flexible substrate is lowered. Namely, a write strategy circuit and the like which output signals containing a lot of high-frequency components are provided in the pickup section. Further, to suppress an amount of heat emission from the pickup section, the main sheet section includes a constant-current supply/current consumption circuit that consumes a current not consumed by a laser diode.

Abstract: The integrating circuit of the triangular wave generating circuit includes an operational amplifier and a capacitor. Switch elements are alternatively turned ON and capacitors are alternatively recharged by the currents flowing in constant-current circuits thus obtaining a triangular wave on an output terminal. In this practice, when the voltage on the output terminal reaches ±1 V, comparator circuits (41, 42) and a flip-flop including NAND gates change over the switch elements. The currents flowing in the constant-current circuits are controlled depending on the current flowing in a load circuit. The current flowing in the load circuit is controlled by a PLL circuit including a phase comparator circuit, a loop filter, an LPF, an operational amplifier and an FET. This provides an output triangular wave having the same frequency as a clock pulse (CK).

Abstract: A pulse-width modulation circuit comprises a comparator having hysteresis characteristics of positive feedback, and an integrator, whose integrated output is compared with an input signal to produce a pulse-width modulation (PWM) signal having an advanced phase characteristic due to differentiation of the input signal. A switching circuit amplifies the pulse-width modulation signal based on the positive and negative source voltages (VPX, VMX). The amplified pulse-width modulation signal is supplied to a speaker via an LC filter, and it is also negatively fed back to the pulse-width modulation circuit. Since the pulse-width modulation signal whose phase is advanced is transmitted through the LC filter, it is possible to reduce phase revolution in the output of the power amplifier circuit. Thus, it is possible to effect negative feedback on the pulse-width modulation signal in a stable manner.

Abstract: The integrating circuit of the triangular wave generating circuit includes an operational amplifier and a capacitor. Switch elements are alternatively turned ON and capacitors are alternatively recharged by the currents flowing in constant-current circuits thus obtaining a triangular wave on an output terminal. In this practice, when the voltage on the output terminal reaches ±1 V, comparator circuits (41, 42) and a flip-flop including NAND gates change over the switch elements. The currents flowing in the constant-current circuits are controlled depending on the current flowing in a load circuit. The current flowing in the load circuit is controlled by a PLL circuit including a phase comparator circuit, a loop filter, an LPF, an operational amplifier and an FET. This provides an output triangular wave having the same frequency as a clock pulse (CK).

Abstract: An input signal (SIN) is inverted by an inverter (101), and the inverted input signal is entered into a tri-state type inverter (104). An output portion of this inverter is connected via a delay path (105) to an input portion of an operational amplifier (106). This operational amplifier owns a hysteresis characteristic with respect to a signal entered thereinto. An exclusive-OR gate circuit (103) controls to set the output state of the inverter to a low impedance state upon receipt of a signal (S11) obtained by inverting the input signal, and controls to set the output state of the inverter to a high impedance state upon receipt of a signal (S16) output from the operational amplifier. As a result, an amplitude of a signal (S15) is limited to a constant amplitude in response to the hysteresis characteristic of the operational amplifier (106), and a delay time is made constant.

Abstract: An operational amplifier has a differential amplifier stage comprising a pair of first PMOS transistors for inputting signals, which are arranged between a positive voltage supply coupled with a first constant current source and a negative voltage supply, wherein second PMOS transistors of a high voltage resistant type, gates of which are biased to a prescribed voltage, are arranged on current paths lying between the first PMOS transistors and the negative voltage supply together with load resistors. Herein, each of drain voltages of the first PMOS transistors is limited to a certain value that is higher than the prescribed voltage by a gate threshold voltage. Therefore, even when the first PMOS transistors are configured of a normal voltage resistant type, it is possible to reliably prevent voltages applied to the first PMOS transistors from exceeding breakdown voltages thereof, thus avoiding unnecessary reduction of an S/N ratio.

Abstract: A laser diode driving circuit is provided, which is capable of supplying a laser diode thereof with a high-speed pulse current. A current source supplies a current to the laser diode. An NMOS transistor as a first switch is connected between the current source and the laser diode. An NMOS transistor as a second switch is connected between a junction between the current source and the first switch and a pseudo load. A controller supplies a first voltage pulse signal to the first switch and a second voltage pulse signal opposite in phase to the first voltage pulse signal to the second switch to switch the first and second switches in a complementary manner.