Patents by Inventor Nobuo Fujiwara
Nobuo Fujiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230147932Abstract: The present disclosure relates a semiconductor device using a super junction structure, and includes: a semiconductor base body of a first conductivity type; a pillar part including a plurality of first pillars of a first conductivity type and a plurality of second pillars of a second conductivity type provided on the semiconductor base body to protrude in a thickness direction of the semiconductor base body; a pillar surrounding part of a first conductivity type or a second conductivity type provided around the pillar part; and a semiconductor element in which the pillar part is provided as an active region, wherein the plurality of first and second pillars have a striped shape in a plan view, and are alternately arranged in parallel to each other in a pillar width direction perpendicular to a longitudinal direction of each of the pillars.Type: ApplicationFiled: June 24, 2020Publication date: May 11, 2023Applicant: Mitsubishi Electric CorporationInventors: Yoichiro TARUI, Nobuo FUJIWARA, Takanori TANAKA
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Patent number: 11189689Abstract: A superjunction layer includes first pillars of a first conductivity type and second pillars of a second conductivity type. First wells are provided respectively on the second pillars to reach the first pillars and are of the second conductivity type. First impurity regions are provided respectively on the first wells and are of the first conductivity type. Second wells are provided respectively on the first pillars, spaced from the second pillars in a section of an active region that is perpendicular to a semiconductor layer, and are of the second conductivity type. Second impurity regions are provided respectively on the second wells and are of the first conductivity type.Type: GrantFiled: October 5, 2017Date of Patent: November 30, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Masayuki Furuhashi, Nobuo Fujiwara, Naoyuki Kawabata
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Publication number: 20200235203Abstract: A superjunction layer includes first pillars of a first conductivity type and second pillars of a second conductivity type. First wells are provided respectively on the second pillars to reach the first pillars and are of the second conductivity type. First impurity regions are provided respectively on the first wells and are of the first conductivity type. Second wells are provided respectively on the first pillars, spaced from the second pillars in a section of an active region that is perpendicular to a semiconductor layer, and are of the second conductivity type. Second impurity regions are provided respectively on the second wells and are of the first conductivity type.Type: ApplicationFiled: October 5, 2017Publication date: July 23, 2020Applicant: Mitsubishi Electric CorporationInventors: Masayuki FURUHASHI, Nobuo FUJIWARA, Naoyuki KAWABATA
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Patent number: 10497850Abstract: A thermoelectric converter includes a substrate and two thermoelectric elements that may include a flat portion and a concave portion. The thermoelectric elements each include one end that contacts with the thermoelectric element and an other end that contacts with thermoelectric element at a bottom surface of the concave portion. The thermoelectric elements are each positioned to be suspended across a space defined by the concave portion. The thermoelectric converter can be manufactured through photolithographic process, and can be incorporated into an exhaust gas recirculation device.Type: GrantFiled: August 25, 2014Date of Patent: December 3, 2019Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Akira Yamashita, Kaoru Motonami, Nobuo Fujiwara, Hidetada Tokioka
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Patent number: 10453951Abstract: A trench-gate semiconductor device including an outside trench, increases reliability of an insulating film at a corner of an open end of the outside trench. The semiconductor device includes: a gate trench reaching an inner part of an n-type drift layer in a cell region; an outside trench outside the cell region; a gate electrode formed inside the gate trench through a gate insulating film; a gate line formed inside the outside trench through an insulating film; and a gate line leading portion formed through the insulating film to cover a corner of an open end of the outside trench closer to the cell region, and electrically connecting the gate electrode to the gate line, and the surface layer of the drift layer in contact with the corner has a second impurity region of p-type that is a part of the well region.Type: GrantFiled: September 9, 2015Date of Patent: October 22, 2019Assignee: Mitsubishi Electric CorporationInventors: Yutaka Fukui, Yasuhiro Kagawa, Kensuke Taguchi, Nobuo Fujiwara, Katsutoshi Sugawara, Rina Tanaka
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Publication number: 20170301788Abstract: A trench-gate semiconductor device including an outside trench, increases reliability of an insulating film at a corner of an open end of the outside trench. The semiconductor device includes: a gate trench reaching an inner part of an n-type drift layer in a cell region; an outside trench outside the cell region; a gate electrode formed inside the gate trench through a gate insulating film; a gate line formed inside the outside trench through an insulating film; and a gate line leading portion formed through the insulating film to cover a corner of an open end of the outside trench closer to the cell region, and electrically connecting the gate electrode to the gate line, and the surface layer of the drift layer in contact with the corner has a second impurity region of p-type that is a part of the well region.Type: ApplicationFiled: September 9, 2015Publication date: October 19, 2017Applicant: Mitsubishi Electric CorporationInventors: Yutaka FUKUI, Yasuhiro KAGAWA, Kensuke TAGUCHI, Nobuo FUJIWARA, Katsutoshi SUGAWARA, Rina TANAKA
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Patent number: 9773874Abstract: A silicon carbide semiconductor device includes trenches formed in a lattice shape on the surface of a silicon carbide substrate on which a semiconductor layer is formed, and gate electrodes formed inside of the trenches via a gate insulating film. The depth of the trenches is smaller in a portion where the trenches are crossingly formed than in a portion where the trenches are formed in parallel to each other. Consequently, the silicon carbide semiconductor device is obtained that increases a withstand voltage between the gate electrodes and corresponding drain electrodes on the semiconductor device rear surface to prevent dielectric breakdown and, at the same time, has a large area of the gate electrodes, high channel density per unit area, and low ON resistance.Type: GrantFiled: July 25, 2013Date of Patent: September 26, 2017Assignee: Mitsubishi Electric CorporationInventors: Nobuo Fujiwara, Yasuhiro Kagawa, Rina Tanaka, Yutaka Fukui
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Patent number: 9691858Abstract: A silicon carbide semiconductor device includes trenches formed in a lattice shape on the surface of a silicon carbide substrate on which a semiconductor layer is formed, and gate electrodes formed inside of the trenches via a gate insulating film. The depth of the trenches is smaller in a portion where the trenches are crossingly formed than in a portion where the trenches are formed in parallel to each other. Consequently, the silicon carbide semiconductor device is obtained that increases a withstand voltage between the gate electrodes and corresponding drain electrodes on the semiconductor device rear surface to prevent dielectric breakdown and, at the same time, has a large area of the gate electrodes, high channel density per unit area, and low ON resistance.Type: GrantFiled: July 25, 2013Date of Patent: June 27, 2017Assignee: Mitsubishi Electric CorporationInventors: Nobuo Fujiwara, Yasuhiro Kagawa, Rina Tanaka, Yutaka Fukui
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Publication number: 20170040522Abstract: A thermoelectric converter includes a substrate and two thermoelectric elements that may include a flat portion and a concave portion. The thermoelectric elements each include one end that contacts with the thermoelectric element and an other end that contacts with thermoelectric element at a bottom surface of the concave portion. The thermoelectric elements are each positioned to be suspended across a space defined by the concave portion. The thermoelectric converter can be manufactured through photolithographic process, and can be incorporated into an exhaust gas recirculation device.Type: ApplicationFiled: August 25, 2014Publication date: February 9, 2017Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Akira YAMASHITA, Kaoru MOTONAMI, Nobuo FUJIWARA, Hidetada TOKIOKA
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Publication number: 20150287789Abstract: A silicon carbide semiconductor device includes trenches formed in a lattice shape on the surface of a silicon carbide substrate on which a semiconductor layer is formed, and gate electrodes formed inside of the trenches via a gate insulating film. The depth of the trenches is smaller in a portion where the trenches are crossingly formed than in a portion where the trenches are formed in parallel to each other. Consequently, the silicon carbide semiconductor device is obtained that increases a withstand voltage between the gate electrodes and corresponding drain electrodes on the semiconductor device rear surface to prevent dielectric breakdown and, at the same time, has a large area of the gate electrodes, high channel density per unit area, and low ON resistance.Type: ApplicationFiled: July 25, 2013Publication date: October 8, 2015Applicant: Mitsubishi Electric CorporationInventors: Nobuo Fujiwara, Yasuhiro Kagawa, Rina Tanaka, Yutaka Fukui
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Publication number: 20090299512Abstract: In the manufacturing system and the manufacturing method of a semiconductor device using a plasma treatment apparatus, a plasma treatment condition is controlled so that a desired shape is obtained after the plasma processing by using a processing shape prediction model for calculating the shape after the plasma processing from the inspection data of a wafer to be treated prior to the treatment and a response surface model for calculating the processing shape depending on a plasma treatment condition. In this configuration, the processing shape prediction model has an adjustable prediction model coefficient, and this prediction model coefficient is automatically calibrated.Type: ApplicationFiled: May 21, 2009Publication date: December 3, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Junichi TANAKA, Masaru KURIHARA, Masaru IZAWA, Hiromasa ARAI, Yoichi NAKAHARA, Takahiro MARUYAMA, Nobuo FUJIWARA
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Publication number: 20060245603Abstract: An audio signal is input to a step-down transformer 11, where it is attenuated by voltage step-down, and then input via a select switch 12 to a variable resistor 13, where it is further attenuated by voltage division.Type: ApplicationFiled: March 23, 2006Publication date: November 2, 2006Applicant: KYODO DENSHI ENGINEERING CO., LTD.Inventors: Nobuyuki Suzuki, Nobuo Fujiwara
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Patent number: 6822334Abstract: A hard mask material 2 such as a silicon oxide film is formed on an aluminum alloy film 3. The hard mask material 2 is patterned in the form of a thick film wiring 6, followed by etching the aluminum alloy film 3 to a given depth through the mask. A resist 5 applied to the thin film portion of the aluminum alloy film 3 is patterned in the form of a thin film wiring 7. Etching through the resist 5 and the hard mask material 2 as a mask is effected to form the thick film wiring 6 and the thin film wiring 7 in the same layer.Type: GrantFiled: January 10, 2001Date of Patent: November 23, 2004Assignee: Renesas Technology Corp.Inventors: Katsunobu Hori, Nobuo Fujiwara, Takashi Watadani, Makoto Nagano
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Publication number: 20020014695Abstract: A hard mask material 2 such as a silicon oxide film is formed on an aluminum alloy film 3. The hard mask material 2 is patterned in the form of a thick film wiring 6, followed by etching the aluminum alloy film 3 to a given depth through the mask. A resist 5 applied to the thin film portion of the aluminum alloy film 3 is patterned in the form of a thin film wiring 7. Etching through the resist 5 and the hard mask material 2 as a mask is effected to form the thick film wiring 6 and the thin film wiring 7 in the same layer.Type: ApplicationFiled: January 10, 2001Publication date: February 7, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Katsunobu Hori, Nobuo Fujiwara, Takashi Watadani, Makoto Nagano
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Patent number: 6232209Abstract: A gate electrode includes a polycrystalline silicon layer, a barrier layer and a metal layer. The metal layer and barrier layer includes for example W and RuO2 layers, respectively. In forming the gate electrode, the metal layer and barrier layer are etched using at least one of the barrier layer and polycrystalline silicon layer as an etching stopper.Type: GrantFiled: November 15, 1999Date of Patent: May 15, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Nobuo Fujiwara, Takahiro Maruyama, Shigenori Sakamori, Akemi Teratani, Satoshi Ogino, Kazuyuki Ohmi, Yuzo Irie
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Patent number: 6156639Abstract: Provided are a method for manufacturing contact structure to prevent, in the wire of a borderless structure, erosion in the contact area between the wire and a conductor. An interlayer insulating film (300) having a wire burying hole is formed and a conductor (400) is buried in the hole. Then, a wire layer (500) covering the hole is formed on the interlayer insulating film (300). The wire layer (500) is made so as to have a borderless structure by using a resist (540) as a mask. A barrier metal layer (510) suppresses erosion in the contact area between the conductor (400) and the wire layer (500).Type: GrantFiled: July 16, 1998Date of Patent: December 5, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuhiro Fukao, Yoshihiro Kusumi, Hiroshi Miyatake, Nobuo Fujiwara, Shigenori Sakamori, Satoshi Iida
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Patent number: 5695597Abstract: Electric field E is generated radially between reaction container and bar-shaped electrode, magnetic field B is formed perpendicular to the electric field, and wafer is disposed perpendicular to magnetic field B. Therefore, the E.times.B drift of plasma generated by magnetron discharge is in the tangential direction of a circle centered at bar-shaped electrode and is parallel to the surface of wafer, whereby maldistribution of plasma in the radial direction is restricted and plasma is distributed uniformly above the main surface of the wafer.Type: GrantFiled: August 17, 1995Date of Patent: December 9, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Nobuo Fujiwara
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Patent number: 5668041Abstract: According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.Type: GrantFiled: April 15, 1996Date of Patent: September 16, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tomonori Okudaira, Takeharu Kuroiwa, Nobuo Fujiwara, Keiichiro Kashihara
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Patent number: 5652186Abstract: According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.Type: GrantFiled: April 15, 1996Date of Patent: July 29, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tomonori Okudaira, Takeharu Kuroiwa, Nobuo Fujiwara, Keiichiro Kashihara
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Patent number: 5534458Abstract: According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.Type: GrantFiled: May 17, 1995Date of Patent: July 9, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tomonori Okudaira, Takeharu Kuroiwa, Nobuo Fujiwara, Keiichiro Kashihara