Patents by Inventor Nobuo Fujiwara

Nobuo Fujiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10417227
    Abstract: A database management system (DBMS) generates a query execution plan including information representing one or more database (DB) operations necessary for executing a query and executes the query based on the query execution plan. In the execution of the query, the DBMS dynamically generates a task for executing a DB operation and executes the dynamically generated task. The DBMS executes a task in a plurality of threads executed by a processor core.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: September 17, 2019
    Assignees: Hitachi, Ltd., The University of Tokyo
    Inventors: Akira Shimizu, Seisuke Tokuda, Michiko Yoshida, Kazuhiko Mogi, Shinji Fujiwara, Nobuo Kawamura, Masaru Kitsuregawa, Kazuo Goda
  • Publication number: 20170301788
    Abstract: A trench-gate semiconductor device including an outside trench, increases reliability of an insulating film at a corner of an open end of the outside trench. The semiconductor device includes: a gate trench reaching an inner part of an n-type drift layer in a cell region; an outside trench outside the cell region; a gate electrode formed inside the gate trench through a gate insulating film; a gate line formed inside the outside trench through an insulating film; and a gate line leading portion formed through the insulating film to cover a corner of an open end of the outside trench closer to the cell region, and electrically connecting the gate electrode to the gate line, and the surface layer of the drift layer in contact with the corner has a second impurity region of p-type that is a part of the well region.
    Type: Application
    Filed: September 9, 2015
    Publication date: October 19, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yutaka FUKUI, Yasuhiro KAGAWA, Kensuke TAGUCHI, Nobuo FUJIWARA, Katsutoshi SUGAWARA, Rina TANAKA
  • Patent number: 9773874
    Abstract: A silicon carbide semiconductor device includes trenches formed in a lattice shape on the surface of a silicon carbide substrate on which a semiconductor layer is formed, and gate electrodes formed inside of the trenches via a gate insulating film. The depth of the trenches is smaller in a portion where the trenches are crossingly formed than in a portion where the trenches are formed in parallel to each other. Consequently, the silicon carbide semiconductor device is obtained that increases a withstand voltage between the gate electrodes and corresponding drain electrodes on the semiconductor device rear surface to prevent dielectric breakdown and, at the same time, has a large area of the gate electrodes, high channel density per unit area, and low ON resistance.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: September 26, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Nobuo Fujiwara, Yasuhiro Kagawa, Rina Tanaka, Yutaka Fukui
  • Patent number: 9691858
    Abstract: A silicon carbide semiconductor device includes trenches formed in a lattice shape on the surface of a silicon carbide substrate on which a semiconductor layer is formed, and gate electrodes formed inside of the trenches via a gate insulating film. The depth of the trenches is smaller in a portion where the trenches are crossingly formed than in a portion where the trenches are formed in parallel to each other. Consequently, the silicon carbide semiconductor device is obtained that increases a withstand voltage between the gate electrodes and corresponding drain electrodes on the semiconductor device rear surface to prevent dielectric breakdown and, at the same time, has a large area of the gate electrodes, high channel density per unit area, and low ON resistance.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: June 27, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Nobuo Fujiwara, Yasuhiro Kagawa, Rina Tanaka, Yutaka Fukui
  • Publication number: 20170040522
    Abstract: A thermoelectric converter includes a substrate and two thermoelectric elements that may include a flat portion and a concave portion. The thermoelectric elements each include one end that contacts with the thermoelectric element and an other end that contacts with thermoelectric element at a bottom surface of the concave portion. The thermoelectric elements are each positioned to be suspended across a space defined by the concave portion. The thermoelectric converter can be manufactured through photolithographic process, and can be incorporated into an exhaust gas recirculation device.
    Type: Application
    Filed: August 25, 2014
    Publication date: February 9, 2017
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akira YAMASHITA, Kaoru MOTONAMI, Nobuo FUJIWARA, Hidetada TOKIOKA
  • Publication number: 20150287789
    Abstract: A silicon carbide semiconductor device includes trenches formed in a lattice shape on the surface of a silicon carbide substrate on which a semiconductor layer is formed, and gate electrodes formed inside of the trenches via a gate insulating film. The depth of the trenches is smaller in a portion where the trenches are crossingly formed than in a portion where the trenches are formed in parallel to each other. Consequently, the silicon carbide semiconductor device is obtained that increases a withstand voltage between the gate electrodes and corresponding drain electrodes on the semiconductor device rear surface to prevent dielectric breakdown and, at the same time, has a large area of the gate electrodes, high channel density per unit area, and low ON resistance.
    Type: Application
    Filed: July 25, 2013
    Publication date: October 8, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Nobuo Fujiwara, Yasuhiro Kagawa, Rina Tanaka, Yutaka Fukui
  • Publication number: 20090299512
    Abstract: In the manufacturing system and the manufacturing method of a semiconductor device using a plasma treatment apparatus, a plasma treatment condition is controlled so that a desired shape is obtained after the plasma processing by using a processing shape prediction model for calculating the shape after the plasma processing from the inspection data of a wafer to be treated prior to the treatment and a response surface model for calculating the processing shape depending on a plasma treatment condition. In this configuration, the processing shape prediction model has an adjustable prediction model coefficient, and this prediction model coefficient is automatically calibrated.
    Type: Application
    Filed: May 21, 2009
    Publication date: December 3, 2009
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Junichi TANAKA, Masaru KURIHARA, Masaru IZAWA, Hiromasa ARAI, Yoichi NAKAHARA, Takahiro MARUYAMA, Nobuo FUJIWARA
  • Publication number: 20060245603
    Abstract: An audio signal is input to a step-down transformer 11, where it is attenuated by voltage step-down, and then input via a select switch 12 to a variable resistor 13, where it is further attenuated by voltage division.
    Type: Application
    Filed: March 23, 2006
    Publication date: November 2, 2006
    Applicant: KYODO DENSHI ENGINEERING CO., LTD.
    Inventors: Nobuyuki Suzuki, Nobuo Fujiwara
  • Patent number: 6822334
    Abstract: A hard mask material 2 such as a silicon oxide film is formed on an aluminum alloy film 3. The hard mask material 2 is patterned in the form of a thick film wiring 6, followed by etching the aluminum alloy film 3 to a given depth through the mask. A resist 5 applied to the thin film portion of the aluminum alloy film 3 is patterned in the form of a thin film wiring 7. Etching through the resist 5 and the hard mask material 2 as a mask is effected to form the thick film wiring 6 and the thin film wiring 7 in the same layer.
    Type: Grant
    Filed: January 10, 2001
    Date of Patent: November 23, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Katsunobu Hori, Nobuo Fujiwara, Takashi Watadani, Makoto Nagano
  • Publication number: 20020014695
    Abstract: A hard mask material 2 such as a silicon oxide film is formed on an aluminum alloy film 3. The hard mask material 2 is patterned in the form of a thick film wiring 6, followed by etching the aluminum alloy film 3 to a given depth through the mask. A resist 5 applied to the thin film portion of the aluminum alloy film 3 is patterned in the form of a thin film wiring 7. Etching through the resist 5 and the hard mask material 2 as a mask is effected to form the thick film wiring 6 and the thin film wiring 7 in the same layer.
    Type: Application
    Filed: January 10, 2001
    Publication date: February 7, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsunobu Hori, Nobuo Fujiwara, Takashi Watadani, Makoto Nagano
  • Patent number: 6232209
    Abstract: A gate electrode includes a polycrystalline silicon layer, a barrier layer and a metal layer. The metal layer and barrier layer includes for example W and RuO2 layers, respectively. In forming the gate electrode, the metal layer and barrier layer are etched using at least one of the barrier layer and polycrystalline silicon layer as an etching stopper.
    Type: Grant
    Filed: November 15, 1999
    Date of Patent: May 15, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Nobuo Fujiwara, Takahiro Maruyama, Shigenori Sakamori, Akemi Teratani, Satoshi Ogino, Kazuyuki Ohmi, Yuzo Irie
  • Patent number: 6156639
    Abstract: Provided are a method for manufacturing contact structure to prevent, in the wire of a borderless structure, erosion in the contact area between the wire and a conductor. An interlayer insulating film (300) having a wire burying hole is formed and a conductor (400) is buried in the hole. Then, a wire layer (500) covering the hole is formed on the interlayer insulating film (300). The wire layer (500) is made so as to have a borderless structure by using a resist (540) as a mask. A barrier metal layer (510) suppresses erosion in the contact area between the conductor (400) and the wire layer (500).
    Type: Grant
    Filed: July 16, 1998
    Date of Patent: December 5, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuhiro Fukao, Yoshihiro Kusumi, Hiroshi Miyatake, Nobuo Fujiwara, Shigenori Sakamori, Satoshi Iida
  • Patent number: 5695597
    Abstract: Electric field E is generated radially between reaction container and bar-shaped electrode, magnetic field B is formed perpendicular to the electric field, and wafer is disposed perpendicular to magnetic field B. Therefore, the E.times.B drift of plasma generated by magnetron discharge is in the tangential direction of a circle centered at bar-shaped electrode and is parallel to the surface of wafer, whereby maldistribution of plasma in the radial direction is restricted and plasma is distributed uniformly above the main surface of the wafer.
    Type: Grant
    Filed: August 17, 1995
    Date of Patent: December 9, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Nobuo Fujiwara
  • Patent number: 5668041
    Abstract: According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.
    Type: Grant
    Filed: April 15, 1996
    Date of Patent: September 16, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tomonori Okudaira, Takeharu Kuroiwa, Nobuo Fujiwara, Keiichiro Kashihara
  • Patent number: 5652186
    Abstract: According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.
    Type: Grant
    Filed: April 15, 1996
    Date of Patent: July 29, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tomonori Okudaira, Takeharu Kuroiwa, Nobuo Fujiwara, Keiichiro Kashihara
  • Patent number: 5534458
    Abstract: According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.
    Type: Grant
    Filed: May 17, 1995
    Date of Patent: July 9, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tomonori Okudaira, Takeharu Kuroiwa, Nobuo Fujiwara, Keiichiro Kashihara
  • Patent number: 5442213
    Abstract: According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.
    Type: Grant
    Filed: June 7, 1994
    Date of Patent: August 15, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tomonori Okudaira, Takeharu Kuroiwa, Nobuo Fujiwara, Keiichiro Kashihara
  • Patent number: 5435886
    Abstract: A method of electron cyclotron resonance plasma etching including generating a constant plasma in a gas in a chamber containing a semiconductor wafer by supplying microwave energy to the chamber continuously and applying a pulsed direct current bias to the semiconductor wafer, wherein the pulsed bias has a period substantially equal to a time constant determined by the capacitance of the semiconductor wafer and the resistance of an ion sheath at the surface of the semiconductor wafer.
    Type: Grant
    Filed: May 23, 1994
    Date of Patent: July 25, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Nobuo Fujiwara, Takahiro Maruyama, Kenji Kawai, Takahiro Hoshiko
  • Patent number: 5304775
    Abstract: Fine processing is performed by using gas which contains halogen in such a manner that halogen ions contributing to an etching process and ions of a light element, the mass of which is smaller than that of the halogen ion and which does not react with a semiconductor wafer, are present in a plasma generated due to electron cyclotron resonance. Since energy in the plasma is in inverse proportion to the mass, the disorder motion of the halogen ions having large mass can be restrained. Therefore, the halogen ions can be made perpendicularly incident upon the surface of the semiconductor wafer. Consequently, etching process revealing high anisotropy can be performed.
    Type: Grant
    Filed: June 6, 1991
    Date of Patent: April 19, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Nobuo Fujiwara, Kyusaku Nishioka, Teruo Shibano
  • Patent number: 5292395
    Abstract: A plasma reaction apparatus has main and auxiliary magnetic field generating coils for generating a magnetic field which has a gradient of no more than 50 gauss/cm in the axial direction and a difference between the axial magnetic field gradient and the magnetic field gradient ten centimeters from the axis of no more than 10 gauss/cm for processing a semiconductor substrate. The plasma reaction apparatus is able to generate a high density, uniform plasma so that the semiconductor substrate is uniformly processed at high speed.
    Type: Grant
    Filed: May 19, 1992
    Date of Patent: March 8, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Nobuo Fujiwara