Patents by Inventor Nobutoshi Fujii

Nobutoshi Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11130299
    Abstract: To suppress occurrence of contamination or damage to a lens. In the present technology, for example, a manufacturing apparatus allows a spacer which is thicker than a height of a lens resin portion protruded from a substrate to be adhered to the substrate. In addition, for example, in the present technology, the manufacturing apparatus molds the lens resin portion inside a through-hole formed in the substrate by using a mold frame configured with two layers of molds and, after molding the lens resin portion, in the state that one mold is adhered to the substrate, the manufacturing apparatus demolds the substrate from the other mold. The present technology can be applied to, for example, a lens-attached substrate, a stacked lens structure, a camera module, a manufacturing apparatus, a manufacturing method, an electronic apparatus, a computer, a program, a storage medium, a system, or the like.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: September 28, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Hiroshi Tazawa, Toshihiro Kurobe, Sotetsu Saito, Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Nobutoshi Fujii, Toshiaki Shiraiwa, Minoru Ishida
  • Patent number: 11107855
    Abstract: A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: August 31, 2021
    Assignee: SONY CORPORATION
    Inventors: Nobutoshi Fujii, Yoshiya Hagimoto, Kenichi Aoyagi, Yoshihisa Kagawa
  • Publication number: 20210265200
    Abstract: Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.
    Type: Application
    Filed: March 8, 2021
    Publication date: August 26, 2021
    Applicant: Sony Corporation
    Inventors: Yoshihisa Kagawa, Kenichi Aoyagi, Yoshiya Hagimoto, Nobutoshi Fujii
  • Publication number: 20210183931
    Abstract: The present disclosure relates to a solid-state imaging element, a manufacturing method, and an electronic apparatus which are capable of further improving a light-blocking effect. The solid-state imaging element having a laminated structure in which a memory substrate, a logic substrate, and a sensor substrate are laminated includes: a through electrode that connects the memory substrate and the sensor substrate in a manner passing through a semiconductor layer of the logic substrate; a light-blocking metal film arranged in a wiring layer included in the logic substrate and provided on the sensor substrate side, and the light-blocking metal film having an opening opened so as to allow the through electrode to pass through; and a contact electrode formed on a bonded surface between the logic substrate and the sensor substrate and used to connect the through electrode to the sensor substrate side.
    Type: Application
    Filed: October 24, 2018
    Publication date: June 17, 2021
    Inventor: NOBUTOSHI FUJII
  • Patent number: 11031431
    Abstract: A semiconductor device including a plurality of substrates that is stacked, each of the substrates including a semiconductor substrate and a multi-layered wiring layer stacked on the semiconductor substrate, the semiconductor substrate having a circuit with a predetermined function formed thereon. Bonding surfaces between two substrates among the plurality of substrates have an electrode junction structure in which electrodes formed on the respective bonding surfaces are joined in direct contact with each other, the electrode junction structure being a structure for electrical connection between the two substrates.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: June 8, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Nobutoshi Fujii, Yoshiya Hagimoto
  • Patent number: 11024658
    Abstract: The present technology relates to techniques of preventing intrusion of moisture into a chip. Various illustrative embodiments include image sensors that include: a substrate; a plurality of layers stacked on the substrate; the plurality of layers including a photodiode layer having a plurality of photodiodes formed on a surface of the photodiode layer; the plurality of layers including at least one layer having a groove formed such that a portion of the at least one layer is excavated; and a transparent resin layer formed above the photodiode layer and formed in the groove. The present technology can be applied to, for example, an image sensor.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: June 1, 2021
    Assignee: SONY CORPORATION
    Inventors: Atsushi Yamamoto, Shinji Miyazawa, Yutaka Ooka, Kensaku Maeda, Yusuke Moriya, Naoki Ogawa, Nobutoshi Fujii, Shunsuke Furuse, Masaya Nagata, Yuichi Yamamoto
  • Patent number: 10991745
    Abstract: A semiconductor device including a device substrate and a readout circuit substrate. The device substrate includes a device region and a peripheral region. In the device region, a wiring layer and a first semiconductor layer including a compound semiconductor material are stacked. The peripheral region is disposed outside the device region. The readout circuit substrate faces the first semiconductor layer with the wiring layer in between, and is electrically coupled to the first semiconductor layer through the wiring layer. The peripheral region of the device substrate has a junction surface with the readout circuit substrate.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: April 27, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Suguru Saito, Nobutoshi Fujii, Ryosuke Matsumoto, Yoshifumi Zaizen, Shuji Manda, Shunsuke Maruyama, Hideo Shimizu
  • Patent number: 10985102
    Abstract: Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: April 20, 2021
    Assignee: Sony Corporation
    Inventors: Yoshihisa Kagawa, Kenichi Aoyagi, Yoshiya Hagimoto, Nobutoshi Fujii
  • Publication number: 20200365639
    Abstract: A deformation of a stacked lens is suppressed. A stacked lens structure has a configuration in which substrates with lenses having a lens disposed on an inner side of a through-hole formed in the substrate are bonded and stacked by direct bonding. The present technique can be applied to a camera module or the like in which a stacked lens structure in which at least three substrates with lenses including first to third substrates with lenses which are substrates with lenses in which a through-hole is formed in the substrate and a lens is formed on an inner side of the through-hole is integrated with a light receiving element, for example.
    Type: Application
    Filed: July 31, 2020
    Publication date: November 19, 2020
    Applicant: Sony Corporation
    Inventors: Hiroyasu MATSUGAI, Hiroyuki ITOU, Suguru SAITO, Keiji OHSHIMA, Masanori IWASAKI, Toshihiko HAYASHI, Shuzo SATO, Nobutoshi FUJII, Hiroshi TAZAWA, Toshiaki SHIRAIWA, Minoru ISHIDA
  • Publication number: 20200350198
    Abstract: The present technology relates to a semiconductor device in which an air gap structure can be formed in any desired region regardless of the layout of metallic wiring lines, a method for manufacturing the semiconductor device, and an electronic apparatus. A first wiring layer and a second wiring layer including a metallic film are stacked via a diffusion preventing film that prevents diffusion of the metallic film. The diffusion preventing film is formed by burying a second film in a large number of holes formed in a first film. At least the first wiring layer includes the metallic film, an air gap, and a protective film formed with the second film on the inner peripheral surface of the air gap, and the opening width of the air gap is equal to the opening width of the holes formed in the first film or is greater than the opening width of the holes. For example, the present technology can be applied to a semiconductor device in which wiring layers are stacked, and the like.
    Type: Application
    Filed: December 28, 2018
    Publication date: November 5, 2020
    Inventors: SUGURU SAITO, NOBUTOSHI FUJII, MASAKI HANEDA, KAZUNORI NAGAHATA
  • Patent number: 10818717
    Abstract: A deformation of a stacked lens is suppressed. A stacked lens structure has a configuration in which substrates with lenses having a lens disposed on an inner side of a through-hole formed in the substrate are bonded and stacked by direct bonding. The present technique can be applied to a camera module or the like in which a stacked lens structure in which at least three substrates with lenses including first to third substrates with lenses which are substrates with lenses in which a through-hole is formed in the substrate and a lens is formed on an inner side of the through-hole is integrated with a light receiving element, for example.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: October 27, 2020
    Assignee: Sony Corporation
    Inventors: Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Masanori Iwasaki, Toshihiko Hayashi, Shuzo Sato, Nobutoshi Fujii, Hiroshi Tazawa, Toshiaki Shiraiwa, Minoru Ishida
  • Patent number: 10804313
    Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: October 13, 2020
    Assignee: Sony Corporation
    Inventors: Yoshihisa Kagawa, Nobutoshi Fujii, Masanaga Fukasawa, Tokihisa Kaneguchi, Yoshiya Hagimoto, Kenichi Aoyagi, Ikue Mitsuhashi
  • Publication number: 20200273897
    Abstract: The present technology relates to techniques of preventing intrusion of moisture into a chip. Various illustrative embodiments include image sensors that include: a substrate; a plurality of layers stacked on the substrate; the plurality of layers including a photodiode layer having a plurality of photodiodes formed on a surface of the photodiode layer; the plurality of layers including at least one layer having a groove formed such that a portion of the at least one layer is excavated; and a transparent resin layer formed above the photodiode layer and formed in the groove. The present technology can be applied to, for example, an image sensor.
    Type: Application
    Filed: March 2, 2020
    Publication date: August 27, 2020
    Applicant: SONY CORPORATION
    Inventors: Atsushi YAMAMOTO, Shinji MIYAZAWA, Yutaka OOKA, Kensaku MAEDA, Yusuke MORIYA, Naoki OGAWA, Nobutoshi FUJII, Shunsuke FURUSE, Masaya NAGATA, Yuichi YAMAMOTO
  • Patent number: 10753551
    Abstract: An electronic component mounting substrate 10A is configured of an electronic component 20, and a mounting substrate 10 mounting the electronic component 20 thereon, in which concave parts 24 are formed on a mounting surface 23 of the electronic component 20 opposite to the mounting substrate 10, a connection part 39 is exposed at the bottom of the concave part 24, and electronic component attachment parts 12 provided on the mounting substrate 10 are soldered to the connection parts 39 provided in the electronic component 20.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: August 25, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Toshiaki Hasegawa, Kenichi Aoyagi, Yoshiya Hagimoto, Nobutoshi Fujii
  • Patent number: 10712543
    Abstract: A positional shift of a lens of a stacked lens structure is reduced. A plurality of through-holes is formed at a position shifted from a first target position on a substrate according to a first shift. A lens is formed on an inner side of each of the through-holes using a first mold in which a plurality of first transfer surfaces is disposed at a position shifted from a predetermined second target position according to a second shift and a second mold in which a plurality of second transfer surfaces is disposed at a position shifted from a predetermined third target position according to a third shift. The plurality of substrates having the lenses formed therein is formed according to direct bonding, and the plurality of stacked substrates is divided. The present technique can be applied to a stacked lens structure or the like, for example.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: July 14, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Kunihiko Hikichi, Koichi Takeuchi, Toshihiro Kurobe, Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Nobutoshi Fujii, Hiroshi Tazawa, Toshiaki Shiraiwa, Minoru Ishida
  • Patent number: 10707258
    Abstract: A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: July 7, 2020
    Assignee: Sony Corporation
    Inventors: Nobutoshi Fujii, Yoshiya Hagimoto, Kenichi Aoyagi, Yoshihisa Kagawa
  • Patent number: 10690814
    Abstract: Influence of chipping in case of dicing a plurality of stacked substrates is reduced. Provided is a semiconductor device where a substrate, in which a groove surrounding a pattern configured with a predetermined circuit or part is formed, is stacked. The present technology can be applied to, for example, a stacked lens structure where through-holes are formed in each substrate and lenses are disposed in inner sides of the through-holes, a camera module where a stacked lens structure and a light-receiving device are incorporated, a solid-state imaging device where a pixel substrate and a control substrate are stacked, and the like.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: June 23, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Toshiaki Shiraiwa, Masaki Okamoto, Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Nobutoshi Fujii, Hiroshi Tazawa, Minoru Ishida
  • Publication number: 20200127039
    Abstract: There is provided a light-receiving device including: a plurality of photoelectric conversion layers including a first photoelectric conversion layer and a second photoelectric conversion layer disposed in respective regions that are different in a planar view; an insulating film that separates the plurality of photoelectric conversion layers from one another; a first inorganic semiconductor material included in the first photoelectric conversion layer; and a second inorganic semiconductor material included in the second photoelectric conversion layer, and different from the first inorganic semiconductor material.
    Type: Application
    Filed: December 19, 2017
    Publication date: April 23, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Suguru SAITO, Nobutoshi FUJII
  • Patent number: 10627549
    Abstract: Substrates with lenses having lenses disposed therein are aligned with high accuracy. A stacked lens structure has a configuration in which substrates with lenses having a lens disposed on an inner side of a through-hole formed in the substrate are direct-bonded and stacked based on an alignment mark. The alignment mark is formed simultaneously with the through-hole. The present technique can be applied to a camera module or the like in which a stacked lens structure in which at least three substrates with lenses including first to third substrates with lenses which are substrates with lenses in which a through-hole is formed in the substrate and a lens is formed on an inner side of the through-hole is integrated with a light receiving element, for example.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: April 21, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Atsushi Yamamoto, Koichi Takeuchi, Toshihiro Kurobe, Hiroyasu Matsugai, Hiroyuki Itou, Suguru Saito, Keiji Ohshima, Nobutoshi Fujii, Hiroshi Tazawa, Toshiaki Shiraiwa, Minoru Ishida
  • Patent number: 10608028
    Abstract: The present technology relates to techniques of preventing intrusion of moisture into a chip. Various illustrative embodiments include image sensors that include: a substrate; a plurality of layers stacked on the substrate; the plurality of layers including a photodiode layer having a plurality of photodiodes formed on a surface of the photodiode layer; the plurality of layers including at least one layer having a groove formed such that a portion of the at least one layer is excavated; and a transparent resin layer formed above the photodiode layer and formed in the groove. The present technology can be applied to, for example, an image sensor.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: March 31, 2020
    Assignee: SONY CORPORATION
    Inventors: Atsushi Yamamoto, Shinji Miyazawa, Yutaka Ooka, Kensaku Maeda, Yusuke Moriya, Naoki Ogawa, Nobutoshi Fujii, Shunsuke Furuse, Masaya Nagata, Yuichi Yamamoto