Patents by Inventor Nobuyuki Mizukoshi

Nobuyuki Mizukoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7697500
    Abstract: A host device according to an embodiment of the present invention sends to a plurality of device units a specific token packet including address information of a first device unit and a general token transmission time derived from an execution time of a plurality of consecutive transactions upon execution of the plurality of consecutive transactions with a first device unit out of the plurality of device units. The first device unit receives the specific token packet to execute the plurality of transactions. The plurality of device units other than the first device unit receive the specific token packet to shift to and stay in a suspend state until the general token transmission time elapses, and then shift to a waiting state after the general token transmission time.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Nobuyuki Mizukoshi
  • Patent number: 7636343
    Abstract: In a wireless ad-hoc communication system according to an embodiment of the invention, a plurality of communication terminals transmit/receive beacons and are synchronized. The wireless ad-hoc communication system includes first and second networks each including one or more communication terminals; and one or more synchronizing terminals. The synchronizing terminals are capable of transmitting/receiving the beacons to/from the communication terminals. In the wireless ad-hoc communication system, at least one of the communication terminals belonging to the first network and at least one of the communication terminals belonging to the second network exist within a reachable range of the beacons from one of the one or more synchronizing terminals to construct one synchronized network with the first network, the second network, and the synchronizing terminals.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: December 22, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Nobuyuki Mizukoshi
  • Publication number: 20080008154
    Abstract: A host device according to an embodiment of the present invention sends to a plurality of device units a specific token packet including address information of a first device unit and a general token transmission time derived from an execution time of a plurality of consecutive transactions upon execution of the plurality of consecutive transactions with a first device unit out of the plurality of device units. The first device unit receives the specific token packet to execute the plurality of transactions. The plurality of device units other than the first device unit receive the specific token packet to shift to and stay in a suspend state until the general token transmission time elapses, and then shift to a waiting state after the general token transmission time.
    Type: Application
    Filed: December 14, 2005
    Publication date: January 10, 2008
    Applicant: NEC Electronics Corporation
    Inventor: Nobuyuki Mizukoshi
  • Patent number: 7139286
    Abstract: An overhead insertion interface unit connected to a high-speed line via a frame processing unit includes a TOH FIFO, a POH FIFO, and a common gate for transmitting a TOH input request and a POH input request to an external device. Each of the FIFOs receives a TOHAV signal together with TOH data and POH data sequentially, and the frame processing unit performs insertion processing. Overhead extraction processing is performed by the reverse of the operations for insertion processing, using the frame processing unit and the overhead extraction interface unit.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: November 21, 2006
    Assignee: Nec Electronics Corporation
    Inventors: Hirotaka Akaike, Nobuyuki Mizukoshi
  • Publication number: 20060245440
    Abstract: In a wireless ad-hoc communication system according to an embodiment of the invention, a plurality of communication terminals transmit/receive beacons and are synchronized. The wireless ad-hoc communication system includes first and second networks each including one or more communication terminals; and one or more synchronizing terminals. The synchronizing terminals are capable of transmitting/receiving the beacons to/from the communication terminals. In the wireless ad-hoc communication system, at least one of the communication terminals belonging to the first network and at least one of the communication terminals belonging to the second network exist within a reachable range of the beacons from one of the one or more synchronizing terminals to construct one synchronized network with the first network, the second network, and the synchronizing terminals.
    Type: Application
    Filed: April 25, 2006
    Publication date: November 2, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Nobuyuki Mizukoshi
  • Patent number: 6567407
    Abstract: In an ATM (Asynchronous Transfer Mode) switch circuit, use efficiencies of address storage memories are increased even when a total number of output ports is increased. The ATM switch circuit is arranged by an ATM cell buffer memory, an ATM cell managing unit, an address storage memory, an empty address managing unit, and also a buffer address managing unit. In this ATM switch circuit, the address storage memory may be commonly used with respect to the output ports. As a result, since the length of the address chain corresponding to the output ports may be adjusted in accordance with the use frequencies of the output ports, the address storage memory can be effectively used, depending upon a plurality of output ports.
    Type: Grant
    Filed: February 22, 1999
    Date of Patent: May 20, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Nobuyuki Mizukoshi
  • Publication number: 20020141455
    Abstract: An overhead insertion interface unit connected to a high-speed line via a frame processing unit includes a TOH FIFO, a POH FIFO, and a common gate for transmitting a TOH input request and a POH input request to an external device. Each of the FIFOs receives a TOHAV signal together with TOH data and POH data sequentially, and the frame processing unit performs insertion processing. Overhead extraction processing is performed by the reverse of the operations for insertion processing, using the frame processing unit and the overhead extraction interface unit.
    Type: Application
    Filed: March 27, 2002
    Publication date: October 3, 2002
    Applicant: NEC Corporation
    Inventors: Hirotaka Akaike, Nobuyuki Mizukoshi
  • Publication number: 20020012350
    Abstract: A communication system is composed of first and second communication unit. The first communication unit sends transmission data, a control sequence, and an extended control sequence. The control sequence is originally defined by a protocol and includes an abort sequence requesting for abortion of the transmission data. The extended control sequence is undefined by the protocol and is provided for requesting an extended operation. The second communication unit receives the transmission data, the control sequence, and the extended control sequence. The second communication unit executes the extended operation in response to the extended control sequence. The extended control sequence includes the abort sequence.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 31, 2002
    Applicant: NEC Corporation
    Inventor: Nobuyuki Mizukoshi
  • Patent number: 6307858
    Abstract: In an ATM cell transmission system having an ATM layer device (1), a data path interface (3) and a plurality of normal PHY (Physical) layer devices (2-0 to 2-M) according to Utopia Level 2 specification, the ATM layer device (1) comprises: a cell buffer (4); FIFO memories (5-0 to 5-M) each corresponding to each of the normal PHY layer devices (2-0 to 2-M); an output controller (5′) for controlling the cell buffer (4) to output an ATM cell to be transmitted through one of the normal PHY layer devices (2-0 to 2-M) into corresponding one of the FIFO memories (5-0 to 5-M) on condition that the ATM cell is stored in the cell buffer (4) and the corresponding one of the FIFO memories (5-0 to 5-M) is not full; and a cell transmission controller (10) for performing polling of the normal PHY layer devices (2-0 to 2-M), designating a selected PHY layer device among the normal PHY layer devices (2-0 to 2-M) which have returned the HIGH level of the cell transmission allowance signal (TxClav) to the polling and wher
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: October 23, 2001
    Assignee: NEC Corporation
    Inventors: Nobuyuki Mizukoshi, Hideo Ishida, Noboru Sato
  • Patent number: 6266324
    Abstract: In an ATM device comprising a switch core 11, a port shaping unit 25 is arranged within the switch core 11 to carry out a port shaping operation. The port shaping unit 25 controls reading timing of each cell stored in a shared buffer 10. Therefore, a delay to absorb the CDV is decided by the reading timing and the port shaping operation is achieved within the ATM device without attaching any additional memories to the ATM device.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: July 24, 2001
    Assignee: NEC Corporation
    Inventors: Kiyoshi Kirino, Nobuyuki Mizukoshi, Hideo Ishida
  • Patent number: 6034959
    Abstract: An ATM switch includes a multi-destination delivery number counter. The counter stores a multi-destination delivery number of each inputted cell according to destination information in the cell correlating the multi-destination delivery number with an idle address where the cell is stored, on every writing of a cell into an idle address of the shared buffer, and decrements the multi-destination delivery number of the cell on every reading of the cell from the shared buffer. The multi-destination delivery numbers of the cells are utilized for management of switching output of the cells from the shared buffer. The multi-destination delivery number counter detects addressing errors to the shared buffer according to the multi-destination delivery numbers, on every inputting or outputting of the cells. According to the ATM switch, both miniaturization of circuit scale of the ATM switch and improvement of reliability of the ATM switch are made possible.
    Type: Grant
    Filed: August 15, 1997
    Date of Patent: March 7, 2000
    Assignee: NEC Corporation
    Inventors: Nobuyuki Mizukoshi, Makoto Tawada
  • Patent number: 5825767
    Abstract: When a multi-cast cell to be sent to a plurality of output ports is inputted, an address pointer designating the address of storage of the multi-cast cell in the shared buffer is re-cued by copying the cell, for instance from a multi-cast cell address buffer, to address buffers for pertinent output ports. The address pointer of this multi-cast cell is preliminarily stored at a time in small capacity buffers for these output ports and then successively transferred to the address buffers during writing of the multi-cast cell. Since cast cells and multi-cast cells are each given a next address pointer designating an address to be next accessed. A single cast cell and a multi-cast cell are chained via an address cell, which indicates that the succeeding cell is a multi-cast cell. The multi-cast cells in the shared buffer are outputted in a logically re-cued form to their pertinent output ports.
    Type: Grant
    Filed: December 4, 1996
    Date of Patent: October 20, 1998
    Assignee: NEC Corporation
    Inventors: Nobuyuki Mizukoshi, Ruixue Fan