Abstract: A semiconductor integrated circuit device includes: a plurality of devices under test formed on a substrate; a selection circuit formed on the substrate which selects two of the plurality of devices under test; a magnitude comparison circuit formed on the substrate which measures an electrical characteristic of the two selected devices under test and makes a magnitude comparison between values of the measured electrical characteristic; an address memory circuit formed on the substrate which stores addresses of the two devices under test between which the magnitude comparison has been made; and a control circuit formed on the substrate and connected to the selection circuit, the magnitude comparison circuit, and the address memory circuit.

Abstract: A semiconductor integrated circuit device includes: a plurality of devices under test formed on a substrate; a selection circuit formed on the substrate which selects two of the plurality of devices under test; a magnitude comparison circuit formed on the substrate which measures an electrical characteristic of the two selected devices under test and makes a magnitude comparison between values of the measured electrical characteristic; an address memory circuit formed on the substrate which stores addresses of the two devices under test between which the magnitude comparison has been made; and a control circuit formed on the substrate and connected to the selection circuit, the magnitude comparison circuit, and the address memory circuit.

Abstract: An evaluation device for evaluating a semiconductor device, used for evaluating electric characteristics of an electrical connection member provided in a vertical direction to a substrate surface, includes a unit circuit having a switching transistor in which a gate thereof connected to a signal line and one of a source and a drain thereof is connected to a first interconnect, and a first resistance element in which one terminal is connected to the other one of the source and the drain of the switching transistor and the other terminal is connected to a second interconnect. The first resistance element constituting each unit circuit includes at least one electrical connection member.

Abstract: An evaluation device for evaluating a semiconductor device, used for evaluating electric characteristics of an electrical connection member provided in a vertical direction to a substrate surface, includes a unit circuit having a switching transistor in which a gate thereof connected to a signal line and one of a source and a drain thereof is connected to a first interconnect, and a first resistance element in which one terminal is connected to the other one of the source and the drain of the switching transistor and the other terminal is connected to a second interconnect. The first resistance element constituting each unit circuit includes at least one electrical connection member.

Abstract: A reference potential generator is constituted of two signal lines 21 and 22; a charge supplier to supply charge to signal lines 21 and 22; connectors 24a and 24b connecting the charge supplier 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a connector 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, "1" or "0" of readout data can be precisely determined.

Abstract: A semiconductor memory device of nonvolatile ferroelectric capable of stable operation without loss of logic voltage "L" data of the memory cell in rewriting operation. To achieve, for example, as shown in FIG. 1, diodes 1, 2 are connected to cell plate lines 39, 40. Therefore, in rewriting operation, if there is a parasitic resistance 3 in the cell plate line 39, it is possible to prevent occurrence of transient phenomenon of temporary transition of the cell plate line 39 to an excessive negative voltage (for example, lower than -1V) which may cause loss of data.

Abstract: A reference potential generator is constituted of two signal lines 21 and 22; a charge supplying circuit to supply charge to signal lines 21 and 22; a first connection circiut 24a and 24b connecting the charge supplying circuit 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a second connection circuit 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, "1" or "0" of readout data can be precisely determined.

Abstract: In a ferroelectric memory of 1T1C configuration in which a memory cell consists of 1 transistor and 1 capacitor per bit, the capacitance of a dummy memory cell capacitor, i.e., the area occupied by the dummy memory cell capacitor is determined based on the capacitive characteristic of a main memory cell capacitor obtained when the main memory cell capacitor was repeatedly operated with both positive voltage and negative voltage until its capacitive characteristic presented no more change. Moreover, not only the main memory cell capacitor but also the dummy memory cell capacitor are operated with both positive voltage and negative voltage by using a power-source voltage, not a ground voltage, as a voltage for resetting the dummy memory cell capacitor. Consequently, the effect of an imprint on the ferroelectric capacitor is reduced, thereby preventing the malfunction of the ferroelectric memory.

Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.

Abstract: A reference potential generator is constituted of two signal lines 21 and 22; a charge supplying means to supply charge to signal lines 21 and 22; a first connection circuit 24a and 24b connecting the charge supplying circuit 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a second connection circuit 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, "1" or "0" of readout data can be precisely determined.

Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.

Abstract: A memory cell comprises a ferroelectric capacitor, first main memory cells are connected to a first bit line, a first reference memory cell is connected to a second bit line, second main memory cells are connected to the second bit line, and a second reference memory cell is connected to the first bit line. When a first operation mode is selected by a control circuit comprising NAND gates and NOR gates, first main memory cells and first reference memory cell are selected, and when a second operation mode is selected, first main memory cells and second main memory cells are selected. Thus, by switching the operation between the two operation modes, a ferroelectric memory device that has stable operation at a low voltage and high integration at a high voltage is provided.

Abstract: Herein disclosed is a semiconductor integrated circuit device comprising an SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs, and a method of forming this device. The gate electrodes of the drive MISFETs and of the transfer MISFETs of the memory cell, and the word lines, are individually formed of different conductive layers. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The source line is formed of a conductive layer identical to that of the word line. An oxidation resisting film is formed on the gate electrodes of the drive MISFETs so as to reduce stress caused by oxidization of edge portions of these gate electrodes, and to reduce a resulting leakage current.

Abstract: A method is provided for manufacturing a semiconductor integrated circuit device which includes a capacitor element having a first electrode, a second electrode, and a dielectric film formed between said first electrode and said second electrode. In particular, the method includes the step of forming at least one of the first electrode and second electrode with a polycrystalline silicon film which is deposited over a semiconductor substrate by a CVD method and which is doped with an impurity during said deposition to decrease the resistance of the polycrystalline silicon film. The capacitor element formed by this method is particularly useful for memory cells of static random access memory devices.

Abstract: In a ferroelectric memory device comprising a ferroelectric capacitor as the memory cell capacitor, after applying a predetermined electric field to a main body memory cell capacitor C0 or C1 to conduct a writing operation, the electric field applied to the memory cell capacitor C0 or C1 is made zero. The operation is conducted so as not to apply an electric field on the ferroelectric capacitor. As a consequence, characteristic deterioration of the ferroelectric capacitor can be reduced to prevent the malfunction of the ferroelectric memory device.

Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected-with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.

Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.

Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.

Abstract: The life of a semiconductor memory device can be prolonged by using a plurality of memory cells and decreasing the stress applied to the dielectric film of the memory cells storing a data value "1." This is achieved in the present invention by decreasing the number of rewritings required to retain stored data. Specifically, the present invention utilizes a reverse and rewrite means to reverse and rewrite data back into memory cells after being read, memory means for memorizing a signal indicating whether the currently stored data is in a reversed state, and judging means for judging whether the data should be reversely output.

Abstract: A semiconductor memory device comprises a main memory cell, a redundant memory cell, a redundant address data cell comprising a non-volatile memory which electrically memorizes an address of a redundant memory cell which replaced a failed memory cell in the main memory cell, a control circuit 15 and a redundant memory cell selecting circuit 16. The redundant memory cell selecting circuit serves to hold first address data which has been read from the redundant address data cell, and to compare the first address data with second address data for a read or write operation which is input via the control circuit and thereby select the main memory cell or the redundant memory cell.