Patents by Inventor Nobuyuki Shirai

Nobuyuki Shirai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8193578
    Abstract: A power supply circuit includes first and second switching MOSFETS. A semiconductor device, including the second switching MOSFET, has a plurality of transistor cell regions disposed in a semiconductor substrate. A source electrode of the second MOSFET is disposed over a main surface of the semiconductor substrate and is in contact with a top surface of a source region in each of the plurality of transistor cell regions. A drain electrode of the second MOSFET is disposed over a back surface of the semiconductor substrate and is electrically connected to the semiconductor substrate. A Schottky cell region is disposed between the plurality of transistor cell regions in the semiconductor substrate. The source electrode is in contact with a part of the main surface of the semiconductor so as to form a Schottky junction in the Schottky cell region.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: June 5, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura, Yoshito Nakazawa
  • Patent number: 8120102
    Abstract: A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is formed as a film at the same layer level as a source electrode SE electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode GE is constituted of a gate electrode portion G1 formed along a periphery of the chip region CA and a gate finger portion G2 arranged so that the chip region CA is divided into halves along the direction of X. The source electrode SE is constituted of an upper portion and a lower portion, both relative to the gate finger portion G2, and the gate electrode GE and the source electrode SE are connected to a lead frame via a bump electrode.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: February 21, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura
  • Patent number: 8104508
    Abstract: A plug body housing 16 has a receiving recess 17, and the receiving recess 17 includes a first recess 21 opening toward the outside and a second recess 22 connected to the first recess 21. Check valves 8 and 9 are provided in the second recess 22, and a manual valve 14 is provided in the first recess 21. An internal threaded portion 45 is formed in an inner circumferential surface of the first recess 21, and a housing 35 of the manual valve 14 is threaded into the internal threaded portion 45. The check valves 8 and 9 are held between a bottom surface 22a of the second recess 22 and a bottom 35a of the housing 35 so that the check valves 8 and 9 are secured in the second recess 22.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: January 31, 2012
    Assignees: JTEKT Corporation, Toyooki Kogyo Co., Ltd.
    Inventors: Takuya Suzuki, Hidetoshi Fujiwara, Toshihiko Shima, Munetoshi Kuroyanagi, Tadayoshi Kamiya, Soichi Shirai, Nobuyuki Shirai
  • Publication number: 20110309437
    Abstract: To attain reduction in size of a semiconductor device having a power transistor and an SBD, a semiconductor device according to the present invention comprises a first region and a second region formed on a main surface of a semiconductor substrate; plural first conductors and plural second conductors formed in the first and second regions respectively; a first semiconductor region and a second semiconductor region formed between adjacent first conductors in the first region, the second semiconductor region lying in the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region; a third semiconductor region formed between adjacent second conductors in the second region, the third semiconductor region having the same conductivity type as that of the second semiconductor region and being lower in density than the second semiconductor region; a metal formed on the semiconductor substrate in the second region, the third semiconductor region having a metal contact
    Type: Application
    Filed: August 19, 2011
    Publication date: December 22, 2011
    Inventors: NOBUYUKI SHIRAI, Nobuyoshi Matsuura, Yoshito Nakazawa
  • Patent number: 8008714
    Abstract: A semiconductor device, including a MOSFET, has a plurality of transistor cell regions disposed in a semiconductor substrate. A source electrode of the MOSFET is disposed over a main surface of the semiconductor substrate and is in contact with a top surface of a source region in each of the plurality of transistor cell regions. A drain electrode of the MOSFET is a disposed over a back surface of the semiconductor substrate and is electrically connected to the semiconductor substrate. A Schottky cell region is disposed between the plurality of transistor cell regions in the semiconductor substrate. The source electrode is in contact with a part of the main surface of the semiconductor so as to form a Schottky junction in the Schottky cell region.
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: August 30, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura, Yoshito Nakazawa
  • Publication number: 20110079842
    Abstract: A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is formed as a film at the same layer level as a source electrode SE electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode GE is constituted of a gate electrode portion G1 formed along a periphery of the chip region CA and a gate finger portion G2 arranged so that the chip region CA is divided into halves along the direction of X. The source electrode SE is constituted of an upper portion and a lower portion, both relative to the gate finger portion G2, and the gate electrode GE and the source electrode SE are connected to a lead frame via a bump electrode.
    Type: Application
    Filed: December 9, 2010
    Publication date: April 7, 2011
    Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura
  • Publication number: 20110024802
    Abstract: To attain reduction in size of a semiconductor device having a power transistor and an SBD, a semiconductor device according to the present invention comprises a first region and a second region formed on a main surface of a semiconductor substrate; plural first conductors and plural second conductors formed in the first and second regions respectively; a first semiconductor region and a second semiconductor region formed between adjacent first conductors in the first region, the second semiconductor region lying in the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region; a third semiconductor region formed between adjacent second conductors in the second region, the third semiconductor region having the same conductivity type as that of the second semiconductor region and being lower in density than the second semiconductor region; a metal formed on the semiconductor substrate in the second region, the third semiconductor region having a metal contact
    Type: Application
    Filed: October 11, 2010
    Publication date: February 3, 2011
    Inventors: NOBUYUKI SHIRAI, Nobuyoshi Matsuura, Yoshito Nakazawa
  • Publication number: 20110014761
    Abstract: The characteristics of a semiconductor device including a trench-gate power MISFET are improved. The semiconductor device includes a substrate having an active region where the power MISFET is provided and an outer circumferential region which is located circumferentially outside the active region and where a breakdown resistant structure is provided, a pattern formed of a conductive film provided over the substrate in the outer circumferential region with an insulating film interposed therebetween, another pattern isolated from the pattern, and a gate electrode terminal electrically coupled to the gate electrodes of the power MISFET and provided in a layer over the conductive film. The conductive film of the pattern is electrically coupled to the gate electrode terminal, while the conductive film of another pattern is electrically decoupled from the gate electrode terminal.
    Type: Application
    Filed: September 23, 2010
    Publication date: January 20, 2011
    Inventors: Hiroki ARAI, Nobuyuki Shirai, Tsuyoshi Kachi
  • Patent number: 7829946
    Abstract: A semiconductor device including a MOSFET has a plurality of transistor cell regions disposed on a semiconductor substrate and a Schottky cell region disposed between the plurality of transistor cell regions. Each transistor cell region has a plurality of first trenches disposed in a main surface of the semiconductor substrate, a well region between the plurality of first trenches, a first gate insulating film and a first gate electrode of the MOSFET in each first trench, and a source region of the MOSFET in each well region. The Schottky cell region has a plurality of second trenches disposed in the main surface of the semiconductor substrate, a second gate insulating film and a second gate electrode of the MOSFET in each second trench, gate lead-out wiring connected to each second gate electrode, and a plurality of guard ring regions enclosing the respective second trenches.
    Type: Grant
    Filed: March 14, 2009
    Date of Patent: November 9, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura, Yoshito Nakazawa
  • Patent number: 7825480
    Abstract: The characteristics of a semiconductor device including a trench-gate power MISFET are improved. The semiconductor device includes a substrate having an active region where the power MISFET is provided and an outer circumferential region which is located circumferentially outside the active region and where a breakdown resistant structure is provided, a pattern formed of a conductive film provided over the substrate in the outer circumferential region with an insulating film interposed therebetween, another pattern isolated from the pattern, and a gate electrode terminal electrically coupled to the gate electrodes of the power MISFET and provided in a layer over the conductive film. The conductive film of the pattern is electrically coupled to the gate electrode terminal, while the conductive film of another pattern is electrically decoupled from the gate electrode terminal.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: November 2, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroki Arai, Nobuyuki Shirai, Tsuyoshi Kachi
  • Patent number: 7768065
    Abstract: A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is formed as a film at the same layer level as a source electrode SE electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode GE is constituted of a gate electrode portion G1 formed along a periphery of the chip region CA and a gate finger portion G2 arranged so that the chip region CA is divided into halves along the direction of X. The source electrode SE is constituted of an upper portion and a lower portion, both relative to the gate finger portion G2, and the gate electrode GE and the source electrode SE are connected to a lead frame via a bump electrode.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: August 3, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura
  • Publication number: 20100148247
    Abstract: A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is formed as a film at the same layer level as a source electrode SE electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode GE is constituted of a gate electrode portion G1 formed along a periphery of the chip region CA and a gate finger portion G2 arranged so that the chip region CA is divided into halves along the direction of X. The source electrode SE is constituted of an upper portion and a lower portion, both relative to the gate finger portion G2, and the gate electrode GE and the source electrode SE are connected to a lead frame via a bump electrode.
    Type: Application
    Filed: February 19, 2010
    Publication date: June 17, 2010
    Inventors: Nobuyuki SHIRAI, Nobuyoshi Matsuura
  • Patent number: 7659144
    Abstract: Disclosed is a semiconductor device which makes it easy to design a wiring pattern for a wiring substrate on which the semiconductor device is to be mounted. In manufacturing plural semiconductor devices for providing different amounts of output current, arrangements and numbers of leads to which semiconductor chips for power transistors of the semiconductor devices are to be electrically connected are changed according to output current requirements for the semiconductor devices, whereas arrangements and numbers of leads to which semiconductor chips for control circuits of the semiconductor devices are to be electrically connected are fixed to be common to the semiconductor devices. In this way, the probability of malfunction of control circuits (PWM circuits) of the semiconductor devices can be reduced, so that a semiconductor device which makes it easy to design a wiring pattern for a wiring substrate on which the semiconductor device is to be mounted can be provided.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: February 9, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Nobuyuki Shirai, Ryotaro Kudo, Yukihiro Sato
  • Publication number: 20090219002
    Abstract: A capacitor is disposed between the output side and the ground potential of an inductor which creates an output voltage. A first switch element supplies a current from an input voltage to an input side of the inductor, and a second switch element which is turned on when the first switch element is off sets the input side of the inductor to a prescribed potential. A control circuit detects the arrival of the voltage on the input side of the inductor at a high voltage corresponding to the input voltage when the load circuit is in a light load state and the second switch element is off, and turns on the first switch element. It invalidates the detection output of the voltage detecting circuit when the load circuit is in a heavy load state and, after the second switch element is turned off, turns on the first switch element.
    Type: Application
    Filed: May 11, 2009
    Publication date: September 3, 2009
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Nobuyuki Shirai, Ryotaro Kudo
  • Publication number: 20090200608
    Abstract: To attain reduction in size of a semiconductor device having a power transistor and an SBD, a semiconductor device according to the present invention comprises a first region and a second region formed on a main surface of a semiconductor substrate; plural first conductors and plural second conductors formed in the first and second regions respectively; a first semiconductor region and a second semiconductor region formed between adjacent first conductors in the first region, the second semiconductor region lying in the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region; a third semiconductor region formed between adjacent second conductors in the second region, the third semiconductor region having the same conductivity type as that of the second semiconductor region and being lower in density than the second semiconductor region; a metal formed on the semiconductor substrate in the second region, the third semiconductor region having a metal contact
    Type: Application
    Filed: March 14, 2009
    Publication date: August 13, 2009
    Inventors: NOBUYUKI SHIRAI, NOBUYOSHI MATSUURA, YOSHITO NAKAZAWA
  • Patent number: 7547001
    Abstract: In order to obtain a solenoid valve device installed in a gas tank that is small in size and easy to attach to a gas tank, a valve body (8) including a flow passage (a) formed therein to communicate the inside and the outside of a gas tank (1) is inserted to the inside from the outside through a mouth hole (2) of the gas tank (1) and attached to the mouth hole (2). A valve seat (46) is provided in the flow passage (a), and a movable valve element (40) attached to or detached from the valve seat (46) is provided in the valve body (8). A solenoid unit (48) includes a movable core (50) engaged with the valve element (40) and a fixed core (64) facing the movable core (50) to attract the movable core (50) by the energization of a coil (74) and distract the movable core (50) by the non-energization of the coil (74). The solenoid unit (48) is arranged inside a storage hole (16) formed at an end part of the valve body (8) inside the gas tank (1).
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: June 16, 2009
    Assignees: Toyooki Kogyo Co. Ltd., Jtekt Corporation
    Inventors: Tadayoshi Kamiya, Soichi Shirai, Mikio Asai, Nobuyuki Shirai, Yoshiyuki Takeuchi, Toshihiko Shima, Hiroaki Suzuki
  • Patent number: 7548050
    Abstract: A capacitor is disposed between the output side and the ground potential of an inductor which creates an output voltage. A first switch element supplies a current from an input voltage to an input side of the inductor, and a second switch element which is turned on when the first switch element is off sets the input side of the inductor to a prescribed potential. A control circuit detects the arrival of the voltage on the input side of the inductor at a high voltage corresponding to the input voltage when the load circuit is in a light load state and the second switch element is off, and turns on the first switch element. It invalidates the detection output of the voltage detecting circuit when the load circuit is in a heavy load state and, after the second switch element is turned off, turns on the first switch element.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: June 16, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Nobuyuki Shirai, Ryotaro Kudo
  • Publication number: 20090146094
    Abstract: A plug body housing 16 has a receiving recess 17 and the receiving recess 17 includes a first recess 21 opening toward the outside and a second recess 22 connected to the first recess 21. Check valves 8 and 9 are provided in the second recess 22, and a manual valve 14 is provided in the first recess 21. An internal threaded portion 45 is formed in an inner circumferential surface of the first recess 21, and a housing 35 of the manual valve 14 is threaded into the internal threaded portion 45. The check valves 8 and 9 are held between a bottom surface 22a of the second recess 22 and a bottom 35a of the housing 35 so that the check valves 8 and 9 are secured in the second recess 22.
    Type: Application
    Filed: November 10, 2005
    Publication date: June 11, 2009
    Applicant: JTEKT Corporation
    Inventors: Takuya Suzuki, Hidetoshi Fujiwara, Toshihiko Shima, Munetoshi Kuroyanagi, Tadayoshi Kamiya, Soichi Shirai, Nobuyuki Shirai
  • Patent number: 7518208
    Abstract: A semiconductor device has a first region and a second region formed on a surface of a substrate. Plural first conductors and second conductors are formed in the first and second regions respectively. A first semiconductor region and a second semiconductor region are formed between adjacent first conductors. The second semiconductor region is in the first semiconductor region and has a conductivity type opposite to that of the first semiconductor. A third semiconductor region is formed between adjacent second conductors. The third semiconductor region has the same conductivity type as the second semiconductor region and is lower in density than the second semiconductor region. The third semiconductor region has a metal contact region for contact with a metal, which is electrically connected to the second semiconductor region. A center-to-center distance between adjacent first conductors is smaller than that between adjacent second conductors.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: April 14, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura, Yoshito Nakazawa
  • Publication number: 20090008708
    Abstract: The characteristics of a semiconductor device including a trench-gate power MISFET are improved. The semiconductor device includes a substrate having an active region where the power MISFET is provided and an outer circumferential region which is located circumferentially outside the active region and where a breakdown resistant structure is provided, a pattern formed of a conductive film provided over the substrate in the outer circumferential region with an insulating film interposed therebetween, another pattern isolated from the pattern, and a gate electrode terminal electrically coupled to the gate electrodes of the power MISFET and provided in a layer over the conductive film. The conductive film of the pattern is electrically coupled to the gate electrode terminal, while the conductive film of another pattern is electrically decoupled from the gate electrode terminal.
    Type: Application
    Filed: June 4, 2008
    Publication date: January 8, 2009
    Inventors: Hiroki Arai, Nobuyuki Shirai, Tsuyoshi Kachi