Patents by Inventor Nobuyuki Sugii

Nobuyuki Sugii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200126447
    Abstract: An operation motion is accurately determined in an operational information management system. The system includes a motion verification portion that combines and verifies plurality of pieces of sensor information and recognizes a specific body motion, a signal determination portion that determines whether an operation content of an operator is correctly performed based on the body motion recognized by the motion verification portion, and a report portion that reports a determine result of the signal determination portion.
    Type: Application
    Filed: August 23, 2019
    Publication date: April 23, 2020
    Inventors: Hiroyuki YOSHIMOTO, Tetsuya ISHIMARU, Nobuyuki SUGII, Yoshihiro WAKISAKA, Noriyuki HAGA
  • Patent number: 10605824
    Abstract: For the purpose of shortening the MEMS manufacturing TAT, the MEMS manufacturing method according to the present invention includes a step of extracting the first MEMS with first characteristic in a range approximate to the required characteristic from the plurality of MEMS preliminarily prepared on the main surface of the substrate, and a step of forming a second MEMS having the required characteristic by directly processing the first MEMS.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: March 31, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Shuntaro Machida, Nobuyuki Sugii, Keiji Watanabe, Daisuke Ryuzaki, Tetsufumi Kawamura, Kazuki Watanabe
  • Publication number: 20200033390
    Abstract: One preferable aspect of the present invention is a state detecting system which detects a state of a machine device based on a detection signal from a detecting element provided to the machine device, and is the state detecting system which includes a non-normal time rate detecting unit which detects a rate or a value as a non-normal time rate, the rate being a rate of an integration value of a time during which an amplitude of the detection signal exceeds a predetermined normal amplitude within a predetermined time, and the value being physically equivalent to the rate.
    Type: Application
    Filed: June 20, 2019
    Publication date: January 30, 2020
    Inventors: Ryohei MATSUI, Nobuyuki SUGII, Tetsufumi KAWAMURA
  • Patent number: 10410826
    Abstract: The invention is directed to a technique for reducing the time from the start of fabrication of a prototype structure to the completion of fabrication of a real structure. A device processing method includes steps of: fabricating a first structure using an ion beam under a first condition in a first region on a substrate; measuring a size of the first structure which is fabricated; comparing the measurement result with design data; determining a second condition from the comparison result; and fabricating a second structure using the ion beam under the second condition in a second region on the substrate.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: September 10, 2019
    Assignee: HITACHI, LTD.
    Inventors: Tetsufumi Kawamura, Misuzu Sagawa, Kazuki Watanabe, Keiji Watanabe, Shuntaro Machida, Nobuyuki Sugii, Daisuke Ryuzaki
  • Publication number: 20190244659
    Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.
    Type: Application
    Filed: April 17, 2019
    Publication date: August 8, 2019
    Inventors: Shiro KAMOHARA, Yasushi YAMAGATA, Takumi HASEGAWA, Nobuyuki SUGII
  • Patent number: 10336609
    Abstract: First, an ion beam is applied to a workpiece to form a tapered hole the side wall of which is inclined. Next, the application of the ion beam is stopped, and then a material gas is introduced from the gas source to the upper surface of the workpiece from an oblique direction to cause gas molecules to be adsorbed to the upper surface of the workpiece and to the upper portion of the side wall of the hole. Next, introduction of the material gas is stopped, and then the ion beam is applied again to the region of the workpiece where the hole is formed. As a result, at the upper portion of the side wall of the hole, film formation occurs using the gas molecules as the material adsorbed to the side wall of the hole, and, at the bottom portion of the hole, etching of the workpiece occurs.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 2, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Keiji Watanabe, Shuntaro Machida, Katsuya Miura, Aki Takei, Tetsufumi Kawamura, Nobuyuki Sugii, Daisuke Ryuzaki
  • Patent number: 10311943
    Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: June 4, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Shiro Kamohara, Yasushi Yamagata, Takumi Hasegawa, Nobuyuki Sugii
  • Patent number: 10203688
    Abstract: A manufacturing device inputs design information including three-dimensional structure data, generates a manufacturing process flow, and displays the manufacturing process flow on a screen for a user to check, modify, and confirm the flow based on design information and setting information. A process method includes a first process method of a direct modeling method having an FIB method and a second process method of a semiconductor manufacturing process method which is a non-FIB method. The manufacturing device generates a plurality of manufacturing process flows by a combination of cases where each of the process methods is applied to each of the regions of the three-dimensional data. The manufacturing process flow includes a process device, the process method, a control parameter value, a process time, and a total process time for each of process steps. An output unit outputs a manufacturing process flow having, for example, the shortest total process time.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: February 12, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Masaharu Kinoshita, Nobuyuki Sugii, Tomonori Sekiguchi, Shuntaro Machida, Tetsufumi Kawamura
  • Publication number: 20190013179
    Abstract: The invention is directed to a technique for reducing the time from the start of fabrication of a prototype structure to the completion of fabrication of a real structure. A device processing method includes steps of: fabricating a first structure using an ion beam under a first condition in a first region on a substrate; measuring a size of the first structure which is fabricated; comparing the measurement result with design data; determining a second condition from the comparison result; and fabricating a second structure using the ion beam under the second condition in a second region on the substrate.
    Type: Application
    Filed: March 18, 2016
    Publication date: January 10, 2019
    Applicant: HITACHI, LTD.
    Inventors: Tetsufumi KAWAMURA, Misuzu SAGAWA, Kazuki WATANABE, Keiji WATANABE, Shuntaro MACHIDA, Nobuyuki SUGII, Daisuke RYUZAKI
  • Publication number: 20180273378
    Abstract: Provided is a technology that enables the shortening of the designing period. A device designing method includes a step of extracting a structure compatible with requested characteristics from a database in which each structure of a device is associated with characteristics and a step of outputting the extracted structure and a tuning parameter for adjusting the structure into ranges of the requested characteristics. In regard to each structure parameter determining the structure of the device, characteristics obtained by performing a simulation while exhaustively changing the structure parameter in a manufacturable range and the structure parameter used for the simulation are stored in the database while being associated with each other.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 27, 2018
    Inventors: Tetsufumi KAWAMURA, Kazuki WATANABE, Atsushi ISOBE, Yuudai KAMADA, Shuntaro MACHIDA, Nobuyuki SUGII, Daisuke RYUZAKI
  • Publication number: 20180267075
    Abstract: For the purpose of shortening the MEMS manufacturing TAT, the MEMS manufacturing method according to the present invention includes a step of extracting the first MEMS with first characteristic in a range approximate to the required characteristic from the plurality of MEMS preliminarily prepared on the main surface of the substrate, and a step of forming a second MEMS having the required characteristic by directly processing the first MEMS.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 20, 2018
    Inventors: Shuntaro MACHIDA, Nobuyuki SUGII, Keiji WATANABE, Daisuke RYUZAKI, Tetsufumi KAWAMURA, Kazuki WATANABE
  • Publication number: 20180158512
    Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.
    Type: Application
    Filed: February 5, 2018
    Publication date: June 7, 2018
    Inventors: Shiro KAMOHARA, Yasushi YAMAGATA, Takumi HASEGAWA, Nobuyuki SUGII
  • Publication number: 20180137212
    Abstract: Provided is a device design support apparatus in which a data input-output portion receives an input of a first device provisional specification relating to a device from a customer, a database generating portion generates a second database based on a first database stored in a database storing portion and the first device provisional specification, and a device specification generating portion generates a second device provisional specification relating to the device based on the second database, presents the second device provisional specification to the customer by outputting the generated second device provisional specification through the data input-output portion, receives the input of a change content of the second device provisional specification from the customer, and generates a device fixed specification of the device based on the second device provisional specification and the change content.
    Type: Application
    Filed: November 8, 2017
    Publication date: May 17, 2018
    Applicant: HITACHI, LTD.
    Inventors: Yuhua ZHANG, Tetsufumi KAWAMURA, Atsushi ISOBE, Nobuyuki SUGII, Daisuke RYUZAKI
  • Publication number: 20180121589
    Abstract: The present invention provides a technique for determining the circuit configuration and device structure that meet required specifications in a short time. A device design support method includes: a step (S2) of receiving an input of specifications of a sensor, and extracting the circuit configuration and device specification range corresponding to the received specifications of the sensor, by referring to a circuit design database in which the circuit configuration configuring the sensor, the range of the specifications of the device configuring the sensor, and the specifications of the sensor are associated with each other; and a step (S3) of extracting the device structure corresponding to the extracted device specification range by referring to a device design database in which the specifications of the device and the structure of the device are associated with each other.
    Type: Application
    Filed: October 19, 2017
    Publication date: May 3, 2018
    Inventors: Tetsufumi KAWAMURA, Nobuyuki SUGII, Yuudai KAMADA, Yuhua ZHANG, Atsushi ISOBE, Ryohei MATSUI, Daisuke RYUZAKI
  • Publication number: 20180121569
    Abstract: A customer's request is more appropriately reflected in the design. A method of processing a request for designing a device receives a required specification for a device from a user input and output device, searches a case similar to the required specification in the old case specification information, outputs the case similar to the required specification found in the old case specification information to the user input and output device, and calculates a specification of a design result of the device according to the required specification for an unauthorized input for the similar case from the user input and output device, or transmits a request for designing the device according to the required specification to an external design system, and outputs the design result of the device calculated or received from the design system to the user input and output device.
    Type: Application
    Filed: October 17, 2017
    Publication date: May 3, 2018
    Inventors: Futoshi FURUTA, Nobuyuki SUGII, Daisuke RYUZAKI
  • Patent number: 9959924
    Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: May 1, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Shiro Kamohara, Yasushi Yamagata, Takumi Hasegawa, Nobuyuki Sugii
  • Publication number: 20180017958
    Abstract: A manufacturing device inputs design information including three-dimensional structure data, generates a manufacturing process flow, and displays the manufacturing process flow on a screen for a user to check, modify, and confirm the flow based on design information and setting information. A process method includes a first process method of a direct modeling method having an FIB method and a second process method of a semiconductor manufacturing process method which is a non-FIB method. The manufacturing device generates a plurality of manufacturing process flows by a combination of cases where each of the process methods is applied to each of the regions of the three-dimensional data. The manufacturing process flow includes a process device, the process method, a control parameter value, a process time, and a total process time for each of process steps. An output unit outputs a manufacturing process flow having, for example, the shortest total process time.
    Type: Application
    Filed: May 12, 2017
    Publication date: January 18, 2018
    Inventors: Masaharu KINOSHITA, Nobuyuki SUGII, Tomonori SEKIGUCHI, Shuntaro MACHIDA, Tetsufumi KAWAMURA
  • Publication number: 20170362082
    Abstract: First, an ion beam is applied to a workpiece to form a tapered hole the side wall of which is inclined. Next, the application of the ion beam is stopped, and then a material gas is introduced from the gas source to the upper surface of the workpiece from an oblique direction to cause gas molecules to be adsorbed to the upper surface of the workpiece and to the upper portion of the side wall of the hole. Next, introduction of the material gas is stopped, and then the ion beam is applied again to the region of the workpiece where the hole is formed. As a result, at the upper portion of the side wall of the hole, film formation occurs using the gas molecules as the material adsorbed to the side wall of the hole, and, at the bottom portion of the hole, etching of the workpiece occurs.
    Type: Application
    Filed: June 1, 2017
    Publication date: December 21, 2017
    Inventors: Keiji WATANABE, Shuntaro MACHIDA, Katsuya MIURA, Aki TAKEI, Tetsufumi KAWAMURA, Nobuyuki SUGII, Daisuke RYUZAKI
  • Publication number: 20170178717
    Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.
    Type: Application
    Filed: March 3, 2017
    Publication date: June 22, 2017
    Inventors: Shiro KAMOHARA, Yasushi YAMAGATA, Takumi HASEGAWA, Nobuyuki SUGII
  • Patent number: 9646679
    Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: May 9, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Shiro Kamohara, Yasushi Yamagata, Takumi Hasegawa, Nobuyuki Sugii