Patents by Inventor Nodari Sitchinava

Nodari Sitchinava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dynamically reconfigurable shared scan-in test architecture
    Patent number: 7900105
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: March 1, 2011
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Dynamically reconfigurable shared scan-in test architecture
    Patent number: 7836368
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: November 16, 2010
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Dynamically reconfigurable shared scan-in test architecture
    Patent number: 7836367
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: November 16, 2010
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Dynamically Reconfigurable Shared Scan-In Test Architecture
    Publication number: 20100223516
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: May 12, 2010
    Publication date: September 2, 2010
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Dynamically reconfigurable shared scan-in test architecture
    Patent number: 7774663
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: August 10, 2010
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Dynamically reconfigurable shared scan-in test architecture
    Patent number: 7743299
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: June 22, 2010
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Dynamically Reconfigurable Shared Scan-In Test Architecture
    Publication number: 20100031101
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: August 11, 2009
    Publication date: February 4, 2010
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Dynamically Reconfigurable Shared Scan-In Test Architecture
    Publication number: 20090313514
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: August 24, 2009
    Publication date: December 17, 2009
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Dynamically Reconfigurable Shared Scan-In Test Architecture
    Publication number: 20090271673
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: July 9, 2009
    Publication date: October 29, 2009
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Dynamically reconfigurable shared scan-in test architecture
    Patent number: 7596733
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: September 29, 2009
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Dynamically Reconfigurable Shared Scan-In Test Architecture
    Publication number: 20080301510
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: July 23, 2008
    Publication date: December 4, 2008
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Dynamically Reconfigurable Shared Scan-In Test Architecture
    Publication number: 20080294955
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: July 23, 2008
    Publication date: November 27, 2008
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Dynamically reconfigurable shared scan-in test architecture
    Patent number: 7418640
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: August 26, 2008
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Dynamically reconfigurable shared scan-in test architecture
    Publication number: 20050268190
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: May 28, 2004
    Publication date: December 1, 2005
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas Williams