Patents by Inventor Noriaki Suzuki

Noriaki Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080122022
    Abstract: A solid state imaging device comprises: a photoelectric converting portion; a charge transferring portion including a charge transfer electrode for transferring an electric charge generated in the photoelectric converting portion; and a shielding film formed through an insulating film containing nitrogen on the charge transferring portion, wherein the insulating film containing the nitrogen includes: a first insulating film that covers at least a part of an upper surface of the charge transfer electrode; and a second insulating film formed to reach the upper surface of the charge transfer electrode from the photoelectric converting portion, and the first and second insulating films include a discontinuing portion.
    Type: Application
    Filed: November 27, 2007
    Publication date: May 29, 2008
    Inventor: Noriaki SUZUKI
  • Publication number: 20080013750
    Abstract: A sound signal processing apparatus and a sound signal processing method divide an input signal into a low frequency signal output (11) and a high frequency signal output (10), and delay only the high frequency signal output (10), thereby reducing the temporal shift between the high frequency signal and the low frequency signal. Furthermore, correcting the phase of the low frequency signal output (11) in accordance with a change in phase due to the delay of the high frequency signal output (10) allows to prevent variation in frequency characteristics due to interference at the time of addition of the low frequency signal output (11) and the high frequency signal output (10).
    Type: Application
    Filed: June 18, 2007
    Publication date: January 17, 2008
    Inventor: Noriaki Suzuki
  • Publication number: 20070290240
    Abstract: A semiconductor device comprises: an MOS transistor including: a semiconductor substrate; a source region, formed in the semiconductor substrate, that comprises an impurity of a first conductive type; a drain region, formed in the semiconductor substrate, that comprises an impurity of the first conductive type; and a gate electrode, formed through a gate insulating film on the semiconductor substrate, between the source region and the drain region; an impurity region of the first conductive type formed in the semiconductor substrate; an impurity region of a second conductive type to be opposite to the first conductive type formed in the semiconductor substrate; and a wiring provided to connect each of the impurity region of the first conductive type and the impurity region of the second conductive type to the gate electrode.
    Type: Application
    Filed: May 25, 2007
    Publication date: December 20, 2007
    Inventors: Noriaki Suzuki, Masanori Nagase
  • Publication number: 20070275312
    Abstract: A semiconductor device including a test element for a dielectric breakdown test on conductive patterns formed on a semiconductor substrate, wherein the test element includes: a step pattern which is associated with a step portion formed in an underlying layer which is formed on the semiconductor substrate; a conductive pattern adjacent to the step pattern, the conductive pattern being formed by forming a conductive layer on the step pattern and removing at least part of the formed conductive layer selectively by patterning; a pad which is electrically connected to the conductive pattern; and a substrate contact which is electrically connected to the semiconductor substrate.
    Type: Application
    Filed: May 21, 2007
    Publication date: November 29, 2007
    Inventor: Noriaki Suzuki
  • Publication number: 20070242777
    Abstract: A digital amplifier including a clock generation unit configured to output a clock signal, a pulse width modulation unit configured to pulse width-modulate the clock signal based on an input signal, a driving unit configured to alternately drive at least two switching elements which convert the output of the pulse width modulation unit, an analysis unit configured to analyze characteristics of the input signal, and a control unit configured to control frequencies of the clock signal based on an output of the analysis unit.
    Type: Application
    Filed: January 30, 2007
    Publication date: October 18, 2007
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Noriaki Suzuki
  • Patent number: 7184019
    Abstract: A display device such as an LCD having a back light is provided with at least one display setting data group including a message to be displayed and a control command for controlling the switching on and off of the back light. A parameter for selectively specifying a display setting data group is included in the display command. The back light for the LCD is switched on and off, controlled by the control command included in the display setting data group selectively specified by the parameter.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: February 27, 2007
    Assignee: OMRON Corporation
    Inventors: Norihiro Imai, Hiromi Ishihara, Kei Takahashi, Noriaki Suzuki
  • Publication number: 20060221800
    Abstract: A solid-state image pickup element comprises: a semiconductor substrate; an imaging section comprising a photoelectric converting portion, formed on the semiconductor substrate; an intralayer lens formed in an upper layer of the imaging section; and a peripheral circuit section that processes an output of the imaging section, formed on the semiconductor substrate, wherein at least part of the intralayer lens is formed in a lower layer of a wiring portion in the peripheral circuit section.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 5, 2006
    Inventors: Hiroki Takahashi, Noriaki Suzuki
  • Patent number: 7091463
    Abstract: Each transfer electrode of a charge transfer unit is made of a main electrode layer and subsidiary electrode layers formed on the side walls of the main electrode layer. The upper surfaces of the transfer electrodes are flush with each other. A charge coupled device having a practically sufficient charge transfer efficiency can be provided. If this charge coupled device is used for an image pickup apparatus, the distance between photoelectric conversion elements and micro lenses can be shortened.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: August 15, 2006
    Assignee: Fuji Photo Film Co., LTD
    Inventors: Noriaki Suzuki, Kazuaki Ogawa, Tohru Hachiya, Teiji Azumi
  • Publication number: 20030132367
    Abstract: Each transfer electrode of a charge transfer unit is made of a main electrode layer and subsidiary electrode layers formed on the side walls of the main electrode layer. The upper surfaces of the transfer electrodes are flush with each other. A charge coupled device having a practically sufficient charge transfer efficiency can be provided. If this charge coupled device is used for an image pickup apparatus, the distance between photoelectric conversion elements and micro lenses can be shortened.
    Type: Application
    Filed: December 30, 2002
    Publication date: July 17, 2003
    Applicant: FUJI PHOTO FILM CO., LTD.
    Inventors: Noriaki Suzuki, Kazuaki Ogawa, Tohru Hachiya, Teiji Azumi
  • Publication number: 20020122023
    Abstract: A display device such as an LCD having a back light is provided with at least one display setting data group including a message to be displayed and a control command for controlling the switching on and off of the back light. A parameter for selectively specifying a display setting data group is included in the display command. The back light for the LCD is switched on and off, controlled by the control command included in the display setting data group selectively specified by the parameter.
    Type: Application
    Filed: January 30, 2002
    Publication date: September 5, 2002
    Applicant: OMRON Corporation
    Inventors: Norihiro Imai, Hiromi Ishihara, Kei Takahashi, Noriaki Suzuki
  • Patent number: 6118699
    Abstract: That surface portion of a semiconductor substrate which is adjacent to a buried source region formed in the substrate is covered with an offset side wall to suppress expansion of a channel beneath the offset side wall. In addition, buried source regions in the form of offset side walls are formed on the two sides of a drain region having one non-offset side wall to prevent a write or read error in unselected memory cell transistors on both sides of a selected memory transistor either in a data write or in a data read.
    Type: Grant
    Filed: July 13, 1999
    Date of Patent: September 12, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuuichi Tatsumi, Noriaki Suzuki, Hidenobu Minagawa, Kazuhiko Satou, Hitoshi Ohta
  • Patent number: 5538044
    Abstract: Welded steel pipe having wear resistance properties, corrosion resistance and low-temperature toughness is provided by preparing welded steel pipe formed of composite steel material comprised of an outer layer of high-carbon, low-alloy steel and an inner layer having a relatively low carbon content, heating the pipe to a temperature that is not less than 800.degree. C. and not more than 900.degree. C. and then quenching the pipe so as to harden just the high-carbon outer layer, and if necessary this can be followed by reheating at a temperature of not less than 200.degree. C. and not more than 600.degree. C. to thereby produce a pipe with an inner layer having high corrosion resistance and low temperature toughness and an outer layer having high hardness.
    Type: Grant
    Filed: October 4, 1995
    Date of Patent: July 23, 1996
    Assignee: Nippon Steel Corporation
    Inventors: Motofumi Koyuba, Naoki Konno, Noriaki Suzuki
  • Patent number: 5494063
    Abstract: An ultrasonic degreasing apparatus includes a cleaning section, a rinsing section, a hot water cleaning section, and a drying section. The cleaning section has an ultrasonic oscillator for oscillating ultrasonic waves in distilled water and a heater for heating the water, and performs a degreasing process including a cleaning process with respect to an object to be processed in the heated water by using ultrasonic waves. The cleaning section has a deaerating section for performing deaeration by circulating the distilled water. The rinsing section has an ultrasonic oscillator for oscillating ultrasonic waves in distilled water containing a rust preventive and a heater for heating the water, and performs a degreasing process including a rinsing process with respect to the object in the heated water by using the ultrasonic waves. The rinsing section has a deaerating section for performing deaeration by circulating the distilled water.
    Type: Grant
    Filed: March 21, 1995
    Date of Patent: February 27, 1996
    Assignee: NEC Corporation
    Inventors: Katsunori Suzuki, Yoshiaki Ishikawa, Noriaki Suzuki, Mitsutaka Suzuki
  • Patent number: 5380373
    Abstract: The present invention comprises a first process to enclose a floating single crystal thin film with a enclosure material which is hardly affected by an isotropic etchant using a face with the lowest etch rate against an anisotropic etchant as a front surface of a single crystal substrate, a second process to cover a portion of or the entire surface of the single crystal substrate with a cover material which is hardly etched by the anisotropic etchant nor by the isotropic etchant, a third process to form an etched groove by etching and removing a portion of the single crystal substrate in the outer side or under a region enclosed by the enclosure material using the isotropic etchant, and a fourth process to deposit a floating single crystal thin film by etching and removing a portion of the single crystal thin film using the anisotropic etchant and making use of the etched groove.
    Type: Grant
    Filed: July 14, 1993
    Date of Patent: January 10, 1995
    Assignee: Ricoh Seiki Company, Ltd
    Inventors: Mitsuteru Kimura, Noriaki Suzuki
  • Patent number: 5023839
    Abstract: An improved semiconductor memory device having a memory array, a dummy cell and a redundancy cell column is disclosed. At least one dummy capacity cell is connected to the reference bit line to which the dummy cell is connected, and also to a redundancy bit line to which redundancy cells are connected. Therefore, since a capacity on the reference bit line is roughly equalized to that on the redundancy bit line by these dummy capacity cells, it is possible to prevent erroneous potential level determination by a sense amplifier for comparing both the potentials on both the bit lines, without being subjected to the influence of supply voltage fluctuations.
    Type: Grant
    Filed: July 12, 1990
    Date of Patent: June 11, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Noriaki Suzuki, Junichi Miyamoto, Nobuaki Ohtsuka