Patents by Inventor Norikazu Ito

Norikazu Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250098203
    Abstract: A nitride semiconductor device includes a first nitride semiconductor layer that constitutes an electron transit layer, a second nitride semiconductor layer that is formed on the first nitride semiconductor layer, is larger in bandgap than the first nitride semiconductor layer, and constitutes an electron supply layer, and a gate portion that is formed on the second nitride semiconductor layer. The gate portion includes a first semiconductor gate layer of a ridge shape that is disposed on the second nitride semiconductor layer and is constituted of a nitride semiconductor containing an acceptor type impurity, a second semiconductor gate layer that is formed on the first semiconductor gate layer and is constituted of a nitride semiconductor with a larger bandgap than the first semiconductor gate layer, and a gate electrode that is formed on the second semiconductor gate layer and is in Schottky junction with the second semiconductor gate layer.
    Type: Application
    Filed: December 2, 2024
    Publication date: March 20, 2025
    Applicant: ROHM CO., LTD.
    Inventors: Hirotaka OTAKE, Shinya TAKADO, Taketoshi TANAKA, Norikazu ITO
  • Patent number: 12199173
    Abstract: A nitride semiconductor device 1 includes a first nitride semiconductor layer 4 that constitutes an electron transit layer, a second nitride semiconductor layer 5 that is formed on the first nitride semiconductor layer, is larger in bandgap than the first nitride semiconductor layer, and constitutes an electron supply layer, and a gate portion 20 that is formed on the second nitride semiconductor layer. The gate portion 20 includes a first semiconductor gate layer 21 of a ridge shape that is disposed on the second nitride semiconductor layer 5 and is constituted of a nitride semiconductor containing an acceptor type impurity, a second semiconductor gate layer 22 that is formed on the first semiconductor gate layer 21 and is constituted of a nitride semiconductor with a larger bandgap than the first semiconductor gate layer 21, and a gate electrode 23 that is formed on the second semiconductor gate layer 22 and is in Schottky junction with the second semiconductor gate layer 22.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: January 14, 2025
    Assignee: ROHM CO., LTD.
    Inventors: Hirotaka Otake, Shinya Takado, Taketoshi Tanaka, Norikazu Ito
  • Publication number: 20240347603
    Abstract: A nitride semiconductor device includes a low resistance Si substrate that has a first principal surface and a second principal surface opposite thereto, a high resistance Si layer that is formed on the first principal surface and is higher in resistivity than the low resistance Si substrate, and a nitride epitaxial layer that is disposed on the high resistance Si layer.
    Type: Application
    Filed: June 24, 2024
    Publication date: October 17, 2024
    Applicant: ROHM CO., LTD.
    Inventors: Norikazu ITO, Keita SHIKATA, Taketoshi TANAKA
  • Publication number: 20240056028
    Abstract: A method of measuring light and elevated temperature induced degradation includes a first step of injecting carriers into p-type crystalline silicon and maintaining the p-type crystalline silicon at 50° C. or higher and 150° C. or lower until the p-type crystalline silicon has reached a regenerated state, measuring a first degradation amount of the p-type crystalline silicon in the first step, performing a heat treatment on the p-type crystalline silicon at higher than 150° C. and 250° C. or lower, a second step of injecting carriers into the p-type crystalline silicon and maintaining the p-type crystalline silicon at 50° C. or higher and 150° C. or lower until the p-type crystalline silicon has reached a regenerated state, measuring a second degradation amount of the p-type crystalline silicon in the second step, and calculating a light and elevated temperature induced degradation amount of the p-type crystalline silicon based on the first and second degradation amounts.
    Type: Application
    Filed: February 25, 2022
    Publication date: February 15, 2024
    Inventors: Yuji INO, Katsuhiko SHIRASAWA, Hidetaka TAKATO, Shunsuke HEITO, Koichiro NIIRA, Norikazu ITO
  • Publication number: 20240030336
    Abstract: A nitride semiconductor device includes: an electron transport layer constituted by a nitride semiconductor; an electron supply layer formed on the electron transport layer and constituted by a nitride semiconductor that has a larger band gap than the electron transport layer; a gate layer formed on the electron supply layer and constituted by a nitride semiconductor that has a smaller band gap than the electron supply layer and includes an acceptor impurity; a gate electrode formed on the gate layer; and a drain electrode and a source electrode in contact with the electron supply layer. The acceptor impurity includes zinc and magnesium, and the concentration profile of the zinc in the thickness direction of the gate layer is different from the concentration profile of the magnesium in the thickness direction of the gate layer.
    Type: Application
    Filed: October 26, 2021
    Publication date: January 25, 2024
    Applicant: ROHM CO., LTD.
    Inventor: Norikazu ITO
  • Publication number: 20230411508
    Abstract: A nitride semiconductor device includes an electron transit layer that is formed of a nitride semiconductor, an electron supply layer that is formed on the electron transit layer, and formed of a nitride semiconductor and that has a recess which reaches the electron transit layer from a surface, a thermal oxide film that is formed on the surface of the electron transit layer exposed within the recess, a gate insulating film that is embedded within the recess so as to be in contact with the thermal oxide film, a gate electrode that is formed on the gate insulating film and that is opposite to the electron transit layer across the thermal oxide film and the gate insulating film, and a source electrode and a drain electrode that are provided on the electron supply layer at an interval such that the gate electrode intervenes therebetween.
    Type: Application
    Filed: August 18, 2023
    Publication date: December 21, 2023
    Applicant: ROHM CO., LTD.
    Inventors: Kenji YAMAMOTO, Tetsuya FUJIWARA, Minoru AKUTSU, Ken NAKAHARA, Norikazu ITO
  • Patent number: 11777024
    Abstract: A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervene
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: October 3, 2023
    Assignee: ROHM CO., LTD.
    Inventors: Kenji Yamamoto, Tetsuya Fujiwara, Minoru Akutsu, Ken Nakahara, Norikazu Ito
  • Publication number: 20230114315
    Abstract: A nitride semiconductor device includes an electron transit layer, an electron supply layer that is formed on the electron transit layer, a gate layer that is formed on the electron supply layer and contains an Al1-xGaxN (0 < × < 1) based material containing a first impurity, a gate electrode that is formed on the gate layer and is in Schottky junction with the gate layer, and a source electrode and a drain electrode that are electrically connected to the electron supply layer. By this arrangement, a gate withstand voltage can be improved and therefore, a nitride semiconductor device of high reliability can be provided.
    Type: Application
    Filed: April 14, 2021
    Publication date: April 13, 2023
    Inventors: Norikazu ITO, Taketoshi TANAKA, Ken NAKAHARA
  • Publication number: 20220302262
    Abstract: A nitride semiconductor device includes a first impurity layer made of an Al1-XGaXN (0<X?1) based material and containing a first impurity with which a depth of an acceptor level from a valence band (ET-EV) is made not less than 0.3 eV but less than 0.6 eV, an electron transit layer formed on the first impurity layer, an electron supply layer formed on the electron transit layer, agate electrode formed on the electron transit layer, and a source electrode and a drain electrode formed such that the source electrode and the drain electrode sandwich the gate electrode and electrically connected to the electron supply layer.
    Type: Application
    Filed: June 7, 2022
    Publication date: September 22, 2022
    Inventors: Norikazu ITO, Taketoshi TANAKA, Ken NAKAHARA
  • Patent number: 11393905
    Abstract: A nitride semiconductor device includes a first impurity layer made of an Al1-XGaXN (0<X?1) based material and containing a first impurity with which a depth of an acceptor level from a valence band (ET-EV) is made not less than 0.3 eV but less than 0.6 eV, an electron transit layer formed on the first impurity layer, an electron supply layer formed on the electron transit layer, agate electrode formed on the electron transit layer, and a source electrode and a drain electrode formed such that the source electrode and the drain electrode sandwich the gate electrode and electrically connected to the electron supply layer.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: July 19, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Norikazu Ito, Taketoshi Tanaka, Ken Nakahara
  • Patent number: 11365090
    Abstract: An elevator device including on-car presence detection units, each being configured to detect presence of a person on top of a corresponding one of cars, on-car operation panels, each to be operated for a manual operation of the corresponding one of cars, and an elevator control device including a car operation approval unit configured to approve or cancel the operation on the on-car operation panels. When the on-car presence detection units have detected the presence of persons on top of the plurality of cars, the operation on the on-car operation panels of all the cars is canceled by the car operation approval unit. When the on-car presence detection unit has detected the presence of a person on top of one of the plurality of cars, the car operation approval unit approves the operation on the on-car operation panel of any one of the plurality of cars.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: June 21, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Masunori Shibata, Kunimitsu Kishimoto, Takuo Kugiya, Norikazu Ito, Masayuki Kakio
  • Publication number: 20220102543
    Abstract: A nitride semiconductor device 1 includes a first nitride semiconductor layer 4 that constitutes an electron transit layer, a second nitride semiconductor layer 5 that is formed on the first nitride semiconductor layer, is larger in bandgap than the first nitride semiconductor layer, and constitutes an electron supply layer, and a gate portion 20 that is formed on the second nitride semiconductor layer. The gate portion 20 includes a first semiconductor gate layer 21 of a ridge shape that is disposed on the second nitride semiconductor layer 5 and is constituted of a nitride semiconductor containing an acceptor type impurity, a second semiconductor gate layer 22 that is formed on the first semiconductor gate layer 21 and is constituted of a nitride semiconductor with a larger bandgap than the first semiconductor gate layer 21, and a gate electrode 23 that is formed on the second semiconductor gate layer 22 and is in Schottky junction with the second semiconductor gate layer 22.
    Type: Application
    Filed: January 15, 2020
    Publication date: March 31, 2022
    Inventors: Hirotaka OTAKE, Shinya TAKADO, Taketoshi TANAKA, Norikazu ITO
  • Publication number: 20220094326
    Abstract: A piezoelectric element includes a single crystal piezoelectric film, wherein the single crystal piezoelectric film includes an aluminum nitride film and wherein a full width at half maximum at (002) diffraction peak of the aluminum nitride film is smaller than 1.00 degree.
    Type: Application
    Filed: September 14, 2021
    Publication date: March 24, 2022
    Applicant: ROHM CO., LTD.
    Inventors: Noriyuki SHIMOJI, Tomohiro DATE, Norikazu ITO
  • Patent number: 11081617
    Abstract: A solar battery device includes a semiconductor substrate and a covering part. The semiconductor substrate has a first semiconductor region and a second semiconductor region. The first semiconductor region is a first-conductivity-type semiconductor region located on a first surface of the semiconductor substrate. The second semiconductor region is a second-conductivity-type semiconductor region different from the first-conductivity-type and located on a second surface opposite from the first surface. The covering part is located on the first surface of the semiconductor substrate. The covering part has a laminated portion in which a plurality of layers including a passivation layer and an antireflection layer are present in a laminated state. In the laminated portion, the passivation layer includes a region in which a thickness decreases from an outer peripheral portion toward a central part of the first surface.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: August 3, 2021
    Assignee: KYOCERA CORPORATION
    Inventors: Norikazu Ito, Kenji Fukuchi
  • Publication number: 20210217886
    Abstract: A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervene
    Type: Application
    Filed: March 25, 2021
    Publication date: July 15, 2021
    Inventors: Kenji YAMAMOTO, Tetsuya FUJIWARA, Minoru AKUTSU, Ken NAKAHARA, Norikazu ITO
  • Patent number: 11031900
    Abstract: A motor drive apparatus includes: inverter modules equivalent in number to phases of a motor; and a control unit that generates a PWM signal for driving the inverter modules by using PWM. Each of the inverter modules includes: a plurality of pairs of switching elements, each pair of switching elements including two switching elements connected in series; a drive circuit; and a protection circuit. The plurality of pairs of switching elements is connected in parallel, and power GNDs that are reference terminals of the plurality of pairs of switching elements, a control GND that is a reference terminal of the drive circuit, and a terminal for overcurrent fault input in the protection circuit are independently exposed to the outside. The power GNDs and the control GND are connected to a single point on a printed circuit board by a wiring pattern.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: June 8, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Norikazu Ito, Shigeo Umehara, Katsuhiko Saito, Katsuyuki Amano, Masahiro Fukuda
  • Patent number: 10991818
    Abstract: A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervene
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: April 27, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Kenji Yamamoto, Tetsuya Fujiwara, Minoru Akutsu, Ken Nakahara, Norikazu Ito
  • Publication number: 20200365694
    Abstract: A nitride semiconductor device includes a first impurity layer made of an Al1-XGaXN (0<X?1) based material and containing a first impurity with which a depth of an acceptor level from a valence band (ET-EV) is made not less than 0.3 eV but less than 0.6 eV, an electron transit layer formed on the first impurity layer, an electron supply layer formed on the electron transit layer, agate electrode formed on the electron transit layer, and a source electrode and a drain electrode formed such that the source electrode and the drain electrode sandwich the gate electrode and electrically connected to the electron supply layer.
    Type: Application
    Filed: December 21, 2018
    Publication date: November 19, 2020
    Inventors: Norikazu ITO, Taketoshi TANAKA, Ken NAKAHARA
  • Publication number: 20200273975
    Abstract: A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervene
    Type: Application
    Filed: May 12, 2020
    Publication date: August 27, 2020
    Inventors: Kenji YAMAMOTO, Tetsuya FUJIWARA, Minoru AKUTSU, Ken NAKAHARA, Norikazu ITO
  • Patent number: 10749414
    Abstract: A motor driving device that converts alternating-current power to direct-current power and drives a motor, the motor driving device including a printed circuit board having a first plate surface and a second plate surface, having an inverter module and an inverter module provided on the first plate surface, having a first power pattern provided on the second plate surface and connected to the inverter module, having a second power pattern provided on the second plate surface and connected to the inverter module, and having a jumper portion to connect the first power pattern and the second power pattern. A cross-sectional area of the jumper portion is larger than a cross-sectional area of the first power pattern or the second power pattern.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: August 18, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Norikazu Ito, Takuya Shimomugi, Masahiro Fukuda