Patents by Inventor Norikazu Nakamura

Norikazu Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11960096
    Abstract: A head-mounted display device includes an image display unit (300a, 300b) configured to emit image light, a light guide member (100a, 100b) configured to guide the image light and emit the image light to eyes of a wearer who wears the head-mounted display device, and a relay optical system (201a, 201b) arranged between the image display unit and the light guide member, and configured to relay the image light from the image display unit to the light guide member, and form an intermediate image at least once before the image light enters the light guide member.
    Type: Grant
    Filed: December 25, 2018
    Date of Patent: April 16, 2024
    Assignee: RICOH COMPANY, LTD.
    Inventors: Shigenobu Hirano, Yasuo Katano, Kenji Kameyama, Norikazu Igarashi, Satomi Tanaka, Naoki Nakamura
  • Patent number: 10992269
    Abstract: A compound semiconductor device includes a first compound semiconductor layer containing a p-type impurity, a second compound semiconductor layer disposed over the first compound semiconductor layer and containing InGaN, an electron transit layer disposed over the second compound semiconductor layer, and an electron supply layer disposed over the electron transit layer.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: April 27, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, Atsushi Yamada, Junji Kotani, Norikazu Nakamura, Kozo Makiyama
  • Publication number: 20200391444
    Abstract: A three-dimensional object manufacturing method includes steps of: generating, based on three-dimensional data of a three-dimensional object, two-dimensional data for a two-dimensional printed matter in which at least a part of an image appearing on a surface of the three-dimensional object is printed on a medium, and three-dimensional data of a three-dimensional shaped object that includes an attachment groove to which inside the two-dimensional printed matter is attached and forms the three-dimensional object when the two-dimensional printed matter is attached inside the attachment groove (S102); generating the two-dimensional printed matter by a two-dimensional printer based on the two-dimensional data generated in S102 (S103); generating the three-dimensional shaped object by a three-dimensional printer based on three-dimensional data generated in S102 (S104); and generating the three-dimensional object by attaching the two-dimensional printed matter generated in S103 to the inside of the attachment groov
    Type: Application
    Filed: June 3, 2020
    Publication date: December 17, 2020
    Applicant: MIMAKI ENGINEERING CO., LTD.
    Inventors: Kazuya NOZAKI, Norikazu NAKAMURA, Akira IKEDA
  • Patent number: 10847642
    Abstract: Disclosed is a compound semiconductor device that includes an electron transit layer; an electron supply layer disposed above the electron transit layer, and including a first region and a second region, the second region having a composition higher in Al than the first region and covering the first region from at least a bottom part of the second region; a first electrode disposed above the first region; and a second electrode disposed above the second region.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: November 24, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, Junji Kotani, Norikazu Nakamura
  • Patent number: 10651305
    Abstract: A compound semiconductor device includes a substrate, a compound semiconductor layer formed over the substrate, a channel layer formed over the compound semiconductor layer, an electron supply layer formed over the channel layer, and a source electrode, a drain electrode, and a gate electrode that are formed apart from each other over the electron supply layer. A quantum well structure is formed by the compound semiconductor layer, the channel layer, and the electron supply layer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 12, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Junji Kotani, Norikazu Nakamura, Hisao Shigematsu
  • Patent number: 10622469
    Abstract: A compound semiconductor device includes an electron transit layer, a spacer layer disposed on the electron transit layer, and an electron supply layer disposed on the spacer layer and containing a donor impurity. The electron supply layer has a concentration distribution of the donor impurity where the donor impurity is at a first concentration at an interface between the electron supply layer and the spacer layer and at a second concentration lower than the first concentration at an upper surface of the electron supply layer, and a concentration of the donor impurity at one of arbitrarily-selected two positions closer to the upper surface in a thickness direction of the electron supply layer is less than the concentration of the donor impurity at another one of the two positions closer to the interface in the thickness direction.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: April 14, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Junji Kotani, Norikazu Nakamura
  • Patent number: 10600901
    Abstract: A compound semiconductor device includes: a carrier transit layer; a carrier supply layer that is formed over the carrier transit layer and is made of InAlN; and a spacer layer that is formed between the carrier transit layer and the carrier supply layer and is made of at least one of AlGaN and InAlGaN.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: March 24, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Junji Kotani, Norikazu Nakamura, Tetsuro Ishiguro
  • Patent number: 10431656
    Abstract: A semiconductor crystal substrate includes a first buffer layer formed of a nitride semiconductor over a substrate, a second buffer layer formed of a nitride semiconductor on the first buffer layer, a first semiconductor layer formed of a nitride semiconductor on or over the second buffer layer, and a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer. The Fe concentration of the first buffer layer is higher than the C concentration of the first buffer layer. The C concentration of the second buffer layer is higher than the Fe concentration of the second buffer layer.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: October 1, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, Atsushi Yamada, Junji Kotani, Norikazu Nakamura
  • Patent number: 10270404
    Abstract: A compound semiconductor device includes: a first layer of nitride semiconductor, the first layer being doped with Fe; a channel layer of nitride semiconductor above the first layer; and a barrier layer of nitride semiconductor above the channel layer, wherein the channel layer includes: a two-dimensional electron gas region in which the two-dimensional electron gas exists; and an Al-containing region between the two-dimensional electron gas region and the first layer, an Al concentration in the Al-containing region being 5×1017 atoms/cm3 or more and less than 1×1019 atoms/cm3.
    Type: Grant
    Filed: September 25, 2016
    Date of Patent: April 23, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, Norikazu Nakamura, Atsushi Yamada
  • Patent number: 10262946
    Abstract: A wiring substrate includes a first wiring structure and a second wiring structure having a higher wiring density. The second wiring structure includes a wiring layer formed on a first insulation layer of the first wiring structure. The wiring layer includes a first wiring pattern, the upper surface of which includes smooth and rough surfaces. A protective film, formed from a conductive material having a higher migration resistance than the wiring layer, covers only the smooth surface and includes a smooth upper surface. A second insulation layer stacked on the first insulation layer covers the wiring layer and the protective film. The smooth surface is continuous with and downwardly recessed from the smooth surface to expose a peripheral portion of the protective film. The second insulation layer covers upper, lower, and side surfaces of the peripheral portion.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: April 16, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Yusuke Gozu, Yuta Sakaguchi, Norikazu Nakamura, Noriyoshi Shimizu
  • Publication number: 20190091723
    Abstract: A method for masking with an inkjet ink, which is applied to a step of coloring a coloring substrate with a dye solution containing a dye in a solvent, is provided. The coloring substrate is colored by permeation of the dye solution. The method includes: a coloring mask forming step of forming a coloring mask which covers a region that is not colored on a surface of the coloring substrate; a dye coloring step of coloring the coloring substrate with the dye solution in a region not covered by the coloring mask; and a mask detaching step of detaching the coloring mask from the coloring substrate after the dye coloring step. In the coloring mask forming step, a mask forming liquid as a liquid for forming the coloring mask is ejected onto the coloring substrate with a liquid ejection head that ejects liquid using an inkjet scheme.
    Type: Application
    Filed: November 26, 2018
    Publication date: March 28, 2019
    Applicant: MIMAKI ENGINEERING CO., LTD.
    Inventors: NORIKAZU NAKAMURA, ISAO TABAYASHI, MASARU OHNISHI
  • Patent number: 10242936
    Abstract: A disclosed semiconductor device includes a buffer layer formed of a compound semiconductor on a substrate, a first semiconductor layer formed of a compound semiconductor on the buffer layer, a second semiconductor layer formed of a compound semiconductor on the first semiconductor layer, a gate electrode, a source electrode, and a drain electrode formed on the second semiconductor layer, and a heat dissipation part formed below the gate electrode. In the semiconductor device, all or part of the second semiconductor layer and the first semiconductor layer is present between the gate electrode and the heat dissipation part, the heat dissipation part includes a heat dissipation layer and a first intermediate layer formed between the heat dissipation layer and both of the buffer layer and first semiconductor layer, and the heat dissipation layer is formed of a material containing carbon.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: March 26, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Junji Kotani, Norikazu Nakamura
  • Publication number: 20190043976
    Abstract: A compound semiconductor device includes a substrate, a compound semiconductor layer formed over the substrate, a channel layer formed over the compound semiconductor layer, an electron supply layer formed over the channel layer, and a source electrode, a drain electrode, and a gate electrode that are formed apart from each other over the electron supply layer. A quantum well structure is formed by the compound semiconductor layer, the channel layer, and the electron supply layer.
    Type: Application
    Filed: July 26, 2018
    Publication date: February 7, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Junji Kotani, Norikazu Nakamura, Hisao Shigematsu
  • Publication number: 20190020318
    Abstract: A compound semiconductor device includes a first compound semiconductor layer containing a p-type impurity, a second compound semiconductor layer disposed over the first compound semiconductor layer and containing InGaN, an electron transit layer disposed over the second compound semiconductor layer, and an electron supply layer disposed over the electron transit layer.
    Type: Application
    Filed: July 11, 2018
    Publication date: January 17, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, Atsushi Yamada, Junji Kotani, Norikazu Nakamura, Kozo Makiyama
  • Publication number: 20190006503
    Abstract: Disclosed is a compound semiconductor device that includes an electron transit layer; an electron supply layer disposed above the electron transit layer, and including a first region and a second region, the second region having a composition higher in Al than the first region and covering the first region from at least a bottom part of the second region; a first electrode disposed above the first region; and a second electrode disposed above the second region.
    Type: Application
    Filed: June 21, 2018
    Publication date: January 3, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, JUNJI KOTANI, NORIKAZU NAKAMURA
  • Publication number: 20180337271
    Abstract: A compound semiconductor device includes an electron transit layer, a spacer layer disposed on the electron transit layer, and an electron supply layer disposed on the spacer layer and containing a donor impurity. The electron supply layer has a concentration distribution of the donor impurity where the donor impurity is at a first concentration at an interface between the electron supply layer and the spacer layer and at a second concentration lower than the first concentration at an upper surface of the electron supply layer, and a concentration of the donor impurity at one of arbitrarily-selected two positions closer to the upper surface in a thickness direction of the electron supply layer is less than the concentration of the donor impurity at another one of the two positions closer to the interface in the thickness direction.
    Type: Application
    Filed: May 10, 2018
    Publication date: November 22, 2018
    Applicant: FUJITSU LIMITED
    Inventors: JUNJI KOTANI, NORIKAZU NAKAMURA
  • Patent number: 10032899
    Abstract: A semiconductor crystal substrate includes a substrate, a first semiconductor layer including a nitride semiconductor and formed over the substrate, a second semiconductor layer including a nitride semiconductor and formed over the first semiconductor layer, a first cap layer formed on the second semiconductor layer, and a second cap layer formed on the first cap layer. Each of the first semiconductor layer and the second semiconductor layer has a single-crystal structure, the first cap layer has one of a single-crystal structure and a polycrystalline structure, and the second cap layer has an amorphous structure.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: July 24, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Junji Kotani, Norikazu Nakamura
  • Patent number: 9997594
    Abstract: A compound semiconductor device includes: a GaN-based channel layer; a barrier layer of nitride semiconductor above the channel layer; and a cap layer of nitride semiconductor above the barrier layer, wherein the cap layer includes: a first region doped with Fe; and a second region above the first region, a concentration of Fe in the second region being lower than a concentration of Fe in the first region.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: June 12, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, Atsushi Yamada, Norikazu Nakamura
  • Patent number: 9981485
    Abstract: When an image is printed by inkjet printing on a print surface of a target medium, an overcoat layer is formed in a more appropriate manner. A printing method uses color ink heads 202 as exemplified colored ink heads, a clear ink head 204, and ultraviolet irradiators 206. The printing method includes a color printing step of printing a print image using a colored ink in at least a partial region on a print surface of a medium 50, a non-colored region clear printing step of applying a UV clear ink for printing in a region at least including a non-colored region in which ink droplets are not discharged in the color printing step, and an overcoat layer forming step of forming an overcoat layer that covers the print image using the UV clear ink in a region covering at least the print image printed in the color printing step.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: May 29, 2018
    Assignee: MIMAKI ENGINEERING CO., LTD.
    Inventors: Akira Ikeda, Norikazu Nakamura, Moe Ito
  • Publication number: 20180093516
    Abstract: A method for manufacturing a transfer sheet capable of forming a coat layer for protecting an image with high positional accuracy is provided. The method includes a step of printing an ink for forming an image on a water-soluble layer by an inkjet method to form an image layer, and a step of printing an ink containing a photocurable compound on the image layer by the inkjet method to form a coat layer, and the water-soluble layer, the image layer, or the coat layer contains a hot-melt inorganic substance.
    Type: Application
    Filed: April 6, 2016
    Publication date: April 5, 2018
    Applicant: MIMAKI ENGINEERING CO., LTD.
    Inventor: Norikazu NAKAMURA