Patents by Inventor Norikazu Yoshida

Norikazu Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11073896
    Abstract: A storage device comprises a nonvolatile memory, a controller that controls access to the nonvolatile memory, and a power circuit that supplies power to the nonvolatile memory and the controller. The power circuit can control the supply of power to at least parts of the nonvolatile memory and at least parts of the controller. The controller executes a data save process when a sleep transition request is received from the host requesting at least one of a plurality of sleep states according to a requested sleep state of the sleep transition request. The controller provides the host with state transition determination information that includes at one of a power consumption amount for a transition to a sleep state from an idle state and power consumption amount for a transition from the sleep state to the idle state.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: July 27, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Mitsuru Anazawa, Norikazu Yoshida, Takashi Yamaguchi
  • Patent number: 10445018
    Abstract: A switch according to an embodiment includes a first PCIe interface that can be connected to a host on the basis of a PCIe standard. In addition, the switch includes a plurality of second PCIe interfaces that can be connected to a plurality of storage devices, respectively, on the basis of the PCIe standard. The switch further includes a control unit that distributes an access request which is comply with an NVMe standard and is transmitted from the host to any one of the plurality of second PCIe interfaces. The distribution includes a process of constructing an NVMe command of the access request and a process of constructing a data transmission descriptor list of the access request.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: October 15, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Yamaguchi, Norikazu Yoshida, Mitsuru Anazawa
  • Publication number: 20190286219
    Abstract: A storage device comprises a nonvolatile memory, a controller that controls access to the nonvolatile memory, and a power circuit that supplies power to the nonvolatile memory and the controller. The power circuit can control the supply of power to at least parts of the nonvolatile memory and at least parts of the controller. The controller executes a data save process when a sleep transition request is received from the host requesting at least one of a plurality of sleep states according to a requested sleep state of the sleep transition request. The controller provides the host with state transition determination information that includes at one of a power consumption amount for a transition to a sleep state from an idle state and power consumption amount for a transition from the sleep state to the idle state.
    Type: Application
    Filed: October 30, 2018
    Publication date: September 19, 2019
    Inventors: Mitsuru ANAZAWA, Norikazu YOSHIDA, Takashi YAMAGUCHI
  • Patent number: 10331552
    Abstract: According to one embodiment, a storage device includes a storage portion storing a first entry, the first entry includes a first translation table corresponding between a first logical address and a first physical address on a nonvolatile memory, and a first state showing that data at the first physical address is a valid as data at the first logical address, and a controller adding a second entry in the storage portion and changing the first state to a second state when receiving a command from a host, the second entry includes a second translation table corresponding between a second logical address and the first physical address, and a third state showing that the first physical address of the second translation table is referring to the first physical address of the first translation table, the second state showing that the first physical address of the first translation table is shared with the first physical address of the second translation table.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: June 25, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Isao Konuma, Norikazu Yoshida
  • Patent number: 10289560
    Abstract: According to one embodiment, a switch module includes a first port with PCIe/NVMe standard being connectable to a host, second ports with PCIe/NVMe standard being connectable to storage devices respectively, and a controller to make the host recognize the storage devices as a virtual storage device.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: May 14, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Norikazu Yoshida, Takashi Yamaguchi
  • Patent number: 10236044
    Abstract: A memory system includes a semiconductor memory and a controller. The controller is configured to perform a read operation on the semiconductor memory in response to a read instruction received from a host. In response to the read instruction that includes a first logical address, the controller converts the first logical address into a first physical address, and issues a read command and a second physical address different from the first physical address, to the semiconductor memory.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: March 19, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Norikazu Yoshida
  • Publication number: 20180277180
    Abstract: A memory system includes a semiconductor memory and a controller. The controller is configured to perform a read operation on the semiconductor memory in response to a read instruction received from a host. In response to the read instruction that includes a first logical address, the controller converts the first logical address into a first physical address, and issues a read command and a second physical address different from the first physical address, to the semiconductor memory.
    Type: Application
    Filed: August 31, 2017
    Publication date: September 27, 2018
    Inventor: Norikazu YOSHIDA
  • Patent number: 10061527
    Abstract: A memory system includes non-volatile memory. The memory system includes a controller that controls data transfer between a host and the non-volatile memory, and a power supply unit that supplies a voltage to the controller. Further, the controller includes a power supply control unit that determines the voltage supplied to a module in the controller on the basis of an operation condition determined with the host. The power supply unit adjusts the voltage supplied to the module in accordance with a command from the power supply control unit.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: August 28, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoon Tze Chin, Norikazu Yoshida, Mitsuru Anazawa
  • Publication number: 20180074757
    Abstract: A switch according to an embodiment includes a first PCIe interface that can be connected to a host on the basis of a PCIe standard. In addition, the switch includes a plurality of second PCIe interfaces that can be connected to a plurality of storage devices, respectively, on the basis of the PCIe standard. The switch further includes a control unit that distributes an access request which is comply with an NVMe standard and is transmitted from the host to any one of the plurality of second PCIe interfaces. The distribution includes a process of constructing an NVMe command of the access request and a process of constructing a data transmission descriptor list of the access request.
    Type: Application
    Filed: March 6, 2017
    Publication date: March 15, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi YAMAGUCHI, Norikazu YOSHIDA, Mitsuru ANAZAWA
  • Publication number: 20180018119
    Abstract: A memory system according to an embodiment includes non-volatile memory. The memory system includes a controller that controls data transfer between a host and the non-volatile memory, and a power supply unit that supplies a voltage to the controller. Further, the controller includes a power supply control unit that determines the voltage supplied to a module in the controller on the basis of an operation condition determined with the host.
    Type: Application
    Filed: September 25, 2017
    Publication date: January 18, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Yoon Tze CHIN, Norikazu YOSHIDA, Mitsuru ANAZAWA
  • Patent number: 9804795
    Abstract: A memory including non-volatile memory. The memory system also includes a controller that controls data transfer between a host and the non-volatile memory, and a power supply unit that supplies a voltage to the controller. Further, the controller includes a power supply control unit that determines the voltage supplied to a module in the controller on the basis of an operation condition determined with the host. The power supply unit adjusts the voltage supplied to the module in accordance with a command from the power supply control unit.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: October 31, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoon Tze Chin, Norikazu Yoshida, Mitsuru Anazawa
  • Publication number: 20170262380
    Abstract: According to one embodiment, a switch module includes a first port with PCIe/NVMe standard being connectable to a host, second ports with PCIe/NVMe standard being connectable to storage devices respectively, and a controller to make the host recognize the storage devices as a virtual storage device.
    Type: Application
    Filed: September 16, 2016
    Publication date: September 14, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Norikazu YOSHIDA, Takashi YAMAGUCHI
  • Publication number: 20170068479
    Abstract: A memory system according to an embodiment includes non-volatile memory. The memory system includes a controller that controls data transfer between a host and the non-volatile memory, and a power supply unit that supplies a voltage to the controller. Further, the controller includes a power supply control unit that determines the voltage supplied to a module in the controller on the basis of an operation condition determined with the host.
    Type: Application
    Filed: March 4, 2016
    Publication date: March 9, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoon Tze CHIN, Norikazu Yoshida, Mitsuru Anazawa
  • Publication number: 20160266802
    Abstract: According to one embodiment, a storage device includes a first nonvolatile memory having first and second physical addresses, a first controller controlling the first nonvolatile memory and storing data associated with a first memory space which is manageable by itself, the first memory space including the first, second and third physical addresses, a second nonvolatile memory having third and fourth physical addresses, a second controller controlling the second nonvolatile memory and storing data associated with a second memory space which is manageable by itself, the second memory space including the second, third and fourth physical addresses, and a signal line connected between the first and second controller.
    Type: Application
    Filed: August 13, 2015
    Publication date: September 15, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Norikazu YOSHIDA, Youhei KOUCHI
  • Publication number: 20160267012
    Abstract: According to one embodiment, a storage device includes a storage portion storing a first entry, the first entry includes a first translation table corresponding between a first logical address and a first physical address on a nonvolatile memory, and a first state showing that data at the first physical address is a valid as data at the first logical address, and a controller adding a second entry in the storage portion and changing the first state to a second state when receiving a command from a host, the second entry includes a second translation table corresponding between a second logical address and the first physical address, and a third state showing that the first physical address of the second translation table is referring to the first physical address of the first translation table, the second state showing that the first physical address of the first translation table is shared with the first physical address of the second translation table.
    Type: Application
    Filed: August 24, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Isao KONUMA, Norikazu Yoshida
  • Publication number: 20160247581
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a memory interface, a storage unit which stores defective memory cell information, and a storage location control unit which creates second data of a second data length longer than a first data length based on an area at a write destination of first data of the first data length, causes the memory interface to write a plurality of second data to the nonvolatile memory, causes the memory interface to read the second data corresponding to the first data instructed to be read from the nonvolatile memory, and restores the first data based on the read second data and the defective memory cell information.
    Type: Application
    Filed: September 9, 2015
    Publication date: August 25, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Riki SUZUKI, Toshikatsu Hida, Tokumasa Hara, Kenichiro Yoshii, Youhei Kouchi, Norikazu Yoshida
  • Patent number: 9412455
    Abstract: According to one embodiment, a data transfer control device complying with a communication protocol which executes an update of information from an attachment device in a predetermined area of a system memory, the device includes a receiving part receiving the information from the attachment device, a transferring part transferring the information in the predetermined area, the information from the transferring part overwritten in the predetermined area sequentially, and a determining part inhibiting a transfer of the information in the transferring part to omit the update of the information in the predetermined area.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: August 9, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makiko Numata, Mitsunori Tadokoro, Norikazu Yoshida, Kohei Oikawa
  • Patent number: 9384123
    Abstract: According to one embodiment, a memory system includes a non-volatile memory, a resource managing unit that reclaims resources associated with the non-volatile memory and increases the resources, when the usage of the resources associated with the non-volatile memory reaches the predetermined amount, a transmission rate setting unit that calculates a setting value of the transmission rate to receive the write data from a host device, and a transmission control unit that receives the write data from the host device and transmits the received write data to the non-volatile memory. The transmission rate setting unit calculates a small setting value when the usage of the resources associated with the non-volatile memory increases. The transmission control unit executes the reception of the write data from the host device at the transmission rate of the setting value, while the resource managing unit reclaims the resources.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: July 5, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshikatsu Hida, Hiroshi Yao, Norikazu Yoshida
  • Patent number: 9141563
    Abstract: According to one embodiment, a command processing device includes a frontend part and a backend part. The frontend part is configured to execute a data communication with respect to a host based on a predetermined communication protocol, and accept a request of an execution of first and second commands from the backend part. The backend part is configured to queue commands including the first and second commands, and execute a data communication according to the first command with respect to an attachment device and a data communication according to the second command with respect to the attachment device in parallel.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: September 22, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuki Kanamori, Norikazu Yoshida
  • Publication number: 20150262696
    Abstract: According to one embodiment, a controller switches modes including a normal operating mode in which power resources of a volatile memory, a data storage unit, and a power control unit are all ON, a first mode in which the power resource of the volatile memory is OFF, and the power resources of the data storage unit and the power control unit are both ON, and a second mode in which the power resources of the volatile memory and the data storage unit are both OFF, and the power resource of the power control unit is ON. Upon receiving a low power consumption instruction command from a host, the controller stores management information to return to the normal operating mode into the volatile storage unit, and shifts the state of the memory system from the normal operating mode to the first mode.
    Type: Application
    Filed: September 3, 2014
    Publication date: September 17, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Akihiro SAKATA, Norikazu YOSHIDA, Toshikatsu HIDA, Yoshikazu TAKEYAMA, Shinichi KANNO